Layout printability optimization using a silicon simulation methodology

Côté, Michel; Hurat, Philippe

doi:10.1109/isqed.2004.1283667

Cited by 24 publications

(12 citation statements)

References 2 publications

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“…The previous works to detect a "large-area" lithography hotspot can be categorized into two types. The first type uses full-layout lithography simulation [17], [19] which is accurate but suffers from high computation complexity. For this reason, the second type uses geometric methods for better efficiency.…”

Section: Introductionmentioning

confidence: 99%

A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection

Wen

Lin

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In advanced IC manufacturing, as the gap increases between lithography optical wavelength and feature size, it becomes challenging to detect problematic layout patterns called lithography hotspot. In this paper, we propose a novel fuzzy matching model which extracts appropriate feature vectors of hotspot and nonhotspot patterns. Our model can dynamically tune appropriate fuzzy regions around known hotspots. Based on this paper, we develop a fast algorithm for lithography hotspot detection with high accuracy of detection and low probability of false-alarm counts. In addition, since higher dimensional size of feature vectors can produce better accuracy but requires longer run time, this paper proposes a grid reduction technique to significantly reduce the CPU run time with very minor impact on the advantages of higher dimensional space. Our results are very encouraging, with average 94.5% accuracy and low false-alarm counts on a set of test benchmarks.

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Section: Introductionmentioning

confidence: 99%

A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection

Wen

Lin

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The shrinking feature size provides larger chip capacity as well as higher chip complexity for circuit designers to work out a more powerful design than ever. However, down-size scaling brings enormous fabricating difficulties below 130 nm technology node [1]. One of these major difficulties is the photo lithography process.…”

Section: Introductionmentioning

confidence: 99%

“…However, these techniques also brings new constraints for circuit design. Hence, there are many additional design rules introduced to ensure the circuit manufacturability in deep submicron (DSM) era [1]. To satisfy those complex design rules and hence to improve circuit manufacturability, simple and regular layout favors chip implementation.…”

Section: Introductionmentioning

confidence: 99%

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture

Chen

Liu

2008

2008 Design, Automation and Test in Europe

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To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploits the wire width flexibilities to trade area for performance. However, many additional design rules, which confine the routing flexibilities, are introduced in nanoscale circuit designs. With the increasing difficulties of fabricating nanoscale circuits, the conventional nonuniform routing architecture becomes clumsy. We propose an uniform dual-rail routing architecture to cope with these new challenges. The proposed architecture exploits the anti-Miller effect between two adjacent wires with the same signal source. Hence, the coupling capacitance between these two wires is reduced. The simulation results demonstrate that our proposed architecture provides a signal propagation channel with similar propagation delay, less crosstalk noise, and less power consumption to the conventional non-uniform routing architecture with moderate routing area overheads. In terms of the properties and the scalabilities, we argue that the uniform dual-rail routing architecture is a wire sizing alternative without incurring layout irregularity and stacked vias overheads.

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“…1. Design rule count by technology node (adapted from [3]). yield problems introduced by new materials, new processes, increased complexity of resolution enhancement techniques (RET), etc.…”

Section: Introductionmentioning

confidence: 99%

A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

Karthikeyan

Fox

Cote

et al. 2008

IEEE Trans. Semicond. Manufact.

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This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.

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Layout printability optimization using a silicon simulation methodology

Abstract: The

Cited by 24 publications

References 2 publications

A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection

A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture

A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

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