Layout synthesis for datapath designs

Abstract

DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and e c i e n t heuristics for placing the cells in a bit-slice, such that the regulariv of datapath circuits is preserved and the number of channels occupied by a control signal is minimized. In addition, we propose a novel window-based heuristic for global routing of multipin nets. VHDL interface makes DPLAYOUT a general tool which can be easily integrated with any high-level synthesis system. This paper describes the heuristics developed for placement and global routing of a single bit-slice. We compared the area and run-time efficiency of the proposed heuristics with conventional methods and the results show a significant improvement.

A regularity-driven fast gridless detailed router for high frequency datapath designs

“…After sorting the pin co-ordinates by Y -coordinate value, assume that the pins of netA are at loca- k ¡ bit pitch (for j 1 2 ¡ ¡ ¡ P and 1 k N 1) The above algorithm can be illustrated by using a slightly modified version of the design shown in Figure 2. Let us assume that in Figure 2, the logic synthesis tool specified names AB, CD, EF, GH, KL, MN, RS and TV for nets LB [3], LB [2], LB [1], LB[0], SB [3], SB [2], SB [1] and SB[0] respectively.…”

“…and NC-3 = SB [3], SB [2], SB [1], SB[0] . Then, IDC identifies an additional cluster: NC-4 = ABC, DEF .…”

“…We continue this process on all candidate clusters until no further merging is possible. In our example, clusters NC-2 and NC-4 get merged to form a new cluster: NC-New = ABC, DEF, SM [1], SM[0] .…”

“…For example, several datapath placement [1], [2] and synthesis [3] techniques have been reported. In [4], the authors introduce a datapath routing methodology.…”