LDMOS implementation in a 0.35 μm BCD technology (BCD6)

Moscatelli, Alessandro; Merlini, A.; Croce, Giuseppe; Galbiati, P.; Contiero, C.

doi:10.1109/ispsd.2000.856835

Cited by 56 publications

(16 citation statements)

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“…7.31a). Modern angled implant techniques also allow forming a graded profile without resorting to the double-diffusion method [39,40]. The doping gradient provides several benefits including an increased V T at the source end, minimizing I off , while keeping a low doping concentration at the drain [41][42][43].…”

Section: Laterally Graded Channel Effectsmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: Laterally Graded Channel Effectsmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…Such Smart Power ICs enable integration of high voltage (HV) devices for operation at greater than 5 V as well as low voltage logic and analog circuits on the same chip. BCD technologies use buried layers (Moscatelli et al, 2000) or alternatively DTI (Deep Trench Isolation) and SOI (SOI-BCD) (Nitta et al, 2006) to isolate high voltage devices. In this way high voltages (up to $100 V) and high currents (up to $10 A) can be provided in combination with low voltage logic and analog circuits.…”

Section: Smart Power Ic Technology Optionsmentioning

confidence: 99%

“…For the values reported in this paper compliance with automotive reliability requirements has also been ensured and we assume that this is the case for the referenced prior art technologies, too. As a typical representative of a leading 0.35 mm BCD technology we have selected ''BCD6'' reported by (Moscatelli et al, 2000). As a typical example for a leading 0.35=0.25 mm BCD-SOI process we have selected the technology reported by (Nitta et al, 2006).…”

Section: Figure Of Merit and Benchmarkingmentioning

confidence: 99%

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Schrems

Knaipp

Enichlmair

et al. 2008

Elektrotech. Inftech.

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Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics.HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded nonvolatile memory.In this work we propose a new 0.35 mm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 mm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM=Flash technology is shown.We also provide first verification results of the scalability of the proposed 0.35 mm HVCMOS technology to 0.18 mm and beyond as well as to currents of up to 8 A.Skalierbare Hochvolt-CMOS-Technologie fü r ,,Smart Power''-und Sensoranwendungen. Die Integration von analogen und digitalen Funktionen bei immer niedrigeren Versorgungsspannungen sowie deren Kombination mitHochvolt-Bauelementen mit Betriebsspannungen von deutlich mehr als 5 V sowie hoher Strombelastbarkeit ermö glicht den Aufbau von ,,Smart Power-Schaltkreisen'', die in modernen elektronischen Systemen nicht mehr wegzudenken sind. HVCMOS(Hochvolt-CMOS)-Technologien ermö glichen bei -im Vergleich zu BCD-Technologien -wesentlich geringeren Herstellungskosten verschiedene HVSpannungsebenen auf einem Chip, sie zeichnen sich auch durch leichte Skalierbarkeit aus, weiters kö nnen nichtflü chtige Speicher einfach integriert werden.In dieser Arbeit wird eine neue 0,35-m-HVCMOS-Technologie vorgestellt, die die bisherigen Grenzen bei der Stromergiebigkeit ü berwindet. Es sind mit BCD vergleichbare Chip-Grö ßen und Rdson-Werte mö glich, dennoch werden nur zwei zusä tzliche Masken benö tigt. Es werden eine Leistungskennzahl fü r den Vergleich solcher Prozesse vorgestellt und die wesentlichen Erfolgsfaktoren dieser Entwicklung diskutiert. Wesentliche Wettbewerbsfaktoren sind dabei eine Lebensdauer von > zehn Jahren, Betriebstemperaturen von 150 C und eine ESD-Festigkeit von >4 kV HBM sowie die Integration eines robusten EEPROM=Flash-Speichers. Es werden auch erste Ergebnisse der Skalierung der Bauelemente nach 0,18 m und kleiner sowie Resultate fü r die Steuerung von Strö men bis zu 8 A dargestellt.

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“…Competitors either use a 0.35 m compatible process flow, but are limited to lower voltages (e.g. [3,4]), or are in the same voltage range but use a larger critical dimension ( [5,6]) and use multi -chip solutions. Figure 2 shows the roadmap and application areas from the cheap 2.4 m HBIMOS technology towards the much more complex 0.35 m QLM I3T80 technology.…”

Section: Essderc 2002mentioning

confidence: 99%

Future Trends in Intelligent Interface Technologies for 42V Battery Automotive Applications

Moens

Bolognesi²,

Delobel³

et al. 2002

32nd European Solid-State Device Research Conference

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This paper describes the emerging needs for future 42V battery automotive applications. To comply with these needs, a new modular 0.35 m based smart power technology is introduced. The I3T80 technology contains various types of DMOS tr ansistors in the range between 15 to 80V. A set of bipolars, a high voltage floating diode, a large array of passive components, floating logic up to 80V and 4kV HBM compatible ESD protection structures are available. In addition, embedded flash memory is offered. The extensive device library together with the robustness of the devices, makes it perfectly suitable for future 42V automotive applications.

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LDMOS implementation in a 0.35 μm BCD technology (BCD6)

Cited by 56 publications

References 0 publications

High-Voltage and Power Transistors

High-Voltage and Power Transistors

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Future Trends in Intelligent Interface Technologies for 42V Battery Automotive Applications

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