LDPC code construction with flexible hardware implementation

Hocevar, D.E.

doi:10.1109/icc.2003.1204466

Cited by 69 publications

(28 citation statements)

References 6 publications

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“…Zhang and Parhi [4] and Mansour and Shanbhag [5], [6] demonstrated that the decoder can be simplified for regular codes based on algebraically constructed Ramanujan graphs. Hocevar [7] showed a flexible hardware implementation of a code based on permutation matrices. This paper studies LDPC codes and proposes a code construction that produces codes with properties favoring hardware implementation along with good BER performance with low error floors.…”

Section: Introductionmentioning

confidence: 99%

Low-density parity-check code constructions for hardware implementation

Liao

Yeo

Nikolić

2004

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

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Abstract-We present several hardware architectures to implement low-density parity-check (LDPC) decoders for codes constructed with hierarchical structure. The proposed hierarchical formulation of the LDPC code allows a structured hardware realization of the decoder. For a fully-parallel implementation, there is reduced routing congestion, allowing implementations for blocks sizes up to 1024 bits in 0.13µm technology. Partially and fully serial implementations benefit greatly from the structure of the code as well, leading to several flexible, efficient architectures. In a general purpose 0.13µm technology, the approximate area required by a 1024-bit fullyparallel LDPC decoder is found to be 12.5mm 2 while a serial decoder can be implemented in an area of 0.15mm 2 .

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Section: Introductionmentioning

confidence: 99%

Low-density parity-check code constructions for hardware implementation

Liao

Yeo

Nikolić

2004

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

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“…Although many architectures have been reported for flexible high speed LDPC decoders [6], [7], [8], [9], there has been much less work on flexible LDPC encoders. A flexible architecture that uses recursion to calculate parity bits was proposed in [10].…”

Section: Introductionmentioning

confidence: 99%

A flexible hardware encoder for systematic low-density parity-check codes

Yasotharan

Carusone

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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Abstract-This paper proposes a flexible low density parity check encoder. This encoder simplifies the calculations found in other flexible encoders by increasing memory usage, allowing for parallelization and faster encoding. The flexibility of this encoder allows it to be used in emerging multi code applications and standards. To evaluate the encoder, a Verilog description was developed and synthesized on an Altera Stratix platform for the IEEE 802.16e WiMAX standard. The implementation used 11,430 logic elements and operated at a maximum clock frequency of 60 MHz. The throughput ranged from 119 Mbps for rate- codes. A speedup of 2.5-6 times is demonstrated compared to the prior art.

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“…1 with g as small as possible; (2) It is a block structured matrix. These two constraints ensure the effective encoder and decoder hardware implementations.…”

Section: Implementation-aware Irregular Code Constructionmentioning

confidence: 99%

“…Since each non-zero block matrix is a right cyclic shift of an identity matrix, the access address for each memory block can be simply generated by a binary counter. We note that this design strategy shares the same basic idea with the state of the art decoder design [1][2][3].…”

Section: Ldpc Decoder Designmentioning

confidence: 99%

“…Consequently, joint design becomes a key in most recent work [1][2][3][4][5]. However, two challenges still remain largely unsolved: (1) Complexity reduction and effective VLSI architecture design for LDPC encoder remain largely unexplored; (2) Given the desired node degree distribution, no systematic method has ever been proposed to construct the code for hardware implementation. The current practice largely relies on handcraft, e.g., the code template presented in [2].…”

Section: Introductionmentioning

confidence: 99%

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Joint code-encoder-decoder design for LDPC coding system VLSI implementation

Zhang

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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This paper presents a design approach for low-density parity-check (LDPC) coding system hardware implementation by jointly conceiving irregular LDPC code construction and VLSI implementations of encoder and decoder. The key idea is to construct good irregular LDPC codes subject to two constraints that ensure the effective LDPC encoder and decoder hardware implementations. We propose a heuristic algorithm to construct such implementationaware irregular LDPC codes that can achieve very good error correction performance. The encoder and decoder hardware architectures are correspondingly presented.

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LDPC code construction with flexible hardware implementation

Cited by 69 publications

References 6 publications

Low-density parity-check code constructions for hardware implementation

Low-density parity-check code constructions for hardware implementation

A flexible hardware encoder for systematic low-density parity-check codes

Joint code-encoder-decoder design for LDPC coding system VLSI implementation

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