Leading one detectors and leading one position detectors - An evolutionary design methodology

Kunaraj, K.; Seshasayanan, R.

doi:10.1109/cjece.2013.6704691

Cited by 19 publications

(9 citation statements)

References 16 publications

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“…The proposed architecture of the 4-bit LOD is simple in comparison as well as with less hardware requirement. It is easily observed that the proposed design is efficient in comparison of reported design [5][6]31]. [37,38] The proposed 8, 16 and 32 bits LOD having a serial connection in arrangement from the MSB 'dn-1' to the LSB 'd0' in comparison of reported LSB d0 to the MSB dn-1.…”

Section: Leading One Detectormentioning

confidence: 99%

“…Logarithmic operations can be converted multiplications operation into additions and divisions into subtractions, respectively, which can save a lot of computation efforts. Leading-One Detector (LOD) design becomes important due to the normalization process in logarithmic multiplication and logarithmic converter [4][5][6]. It is used in logarithmic converters to find the position of the leading one bit with the integral and the fractional parts of a logarithm operation.…”

Section: Introductionmentioning

confidence: 99%

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An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

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Section: Leading One Detectormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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“…One can verify that the worst-case delay of the circuit corresponds to the 4-bit input binary word "0001". F I G U R E 1 A 4-bit leading-one detector [14] In another 4-bit LOD design, the multiplexers are replaced with 2-input logic gates, ithat is, AND, OR, and NOT, to improve the performance by reducing the delay [19]. The higher-level 4-bit LOD as in Figure 1 is used as our main building block for larger LOD designs.…”

Section: Conventional 4-bit Lodsmentioning

confidence: 99%

“…This value is used as the golden result in the comparisons in Figure 12. The Mitchell multiplier with a conventional exact LOD (any of the previously discussed designs, including LOD III, [20], [14], and [19]) achieves 97.76% accuracy. Note that in a 32‐bit design, the inputs and synaptic weights should be scaled to 32‐bit values; however, we scaled them to 20‐bit, 22‐bit, and 32‐bit values ( n in Figure 12) to better show the differences.…”

Section: Applications Of the Lodsmentioning

confidence: 99%

Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing

Ansari

Gandhi

Cockburn

et al. 2021

IET Computers & Digital Tech

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The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading-one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2 d . Additionally, a scaling scheme is proposed that scales up the input N < 2 d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one '1' in that half; otherwise, the less significant half is passed. Our simulation results show that the 32-bit LOD III can be up to 2.8� more energy-efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…The probability of occurrences of the optimum solution increases by increasing the number of generation runs. The shuffling mechanism is primarily introduced to avoid the search algorithm getting struck at a local minimum [ 24 ]. Perhaps the search algorithm sometimes settles to the local minimum point and we call this phenomenon “positional effect” which can be avoided using the proposed “shuffling mechanism.” This shuffling operator totally changes the position of the elite chromosomes while getting replaced as new population for the next iteration.…”

Section: Introductionmentioning

confidence: 99%

An Evolved Wavelet Library Based on Genetic Algorithm

Vaithiyanathan

Seshasayanan

Kunaraj³

et al. 2014

The Scientific World Journal

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As the size of the images being captured increases, there is a need for a robust algorithm for image compression which satiates the bandwidth limitation of the transmitted channels and preserves the image resolution without considerable loss in the image quality. Many conventional image compression algorithms use wavelet transform which can significantly reduce the number of bits needed to represent a pixel and the process of quantization and thresholding further increases the compression. In this paper the authors evolve two sets of wavelet filter coefficients using genetic algorithm (GA), one for the whole image portion except the edge areas and the other for the portions near the edges in the image (i.e., global and local filters). Images are initially separated into several groups based on their frequency content, edges, and textures and the wavelet filter coefficients are evolved separately for each group. As there is a possibility of the GA settling in local maximum, we introduce a new shuffling operator to prevent the GA from this effect. The GA used to evolve filter coefficients primarily focuses on maximizing the peak signal to noise ratio (PSNR). The evolved filter coefficients by the proposed method outperform the existing methods by a 0.31 dB improvement in the average PSNR and a 0.39 dB improvement in the maximum PSNR.

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Leading one detectors and leading one position detectors - An evolutionary design methodology

Cited by 19 publications

References 16 publications

An efficient architecture of iterative logarithm multiplier

An efficient architecture of iterative logarithm multiplier

Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing

An Evolved Wavelet Library Based on Genetic Algorithm

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