Leakage power analysis of a 90nm FPGA

FPGA Architecture: Survey and Challenges

“…Several studies [84,138,178,198] have indicated that between 60%-70% of FPGA dynamic and static power consumption is located in the programmable interconnect. Leakage power is a particular concern since much of the interconnect resources within the FPGA are not actively used following device programming.…”

A Novel Low Leakage Power FPGAs Look-Up Table

“…Most of the early work on low-power FPGAs has focus on dynamic power consumption, however, leakage power can now compose over 50% of total FPGAs power [2]. Recent work has concentrated on reducing the leakage within the routing switch which account for 60%~70% of total FPGAs leakage [3] [4]. The leakage of LUTs which may constitute over 20%~30% of total chip power, however has not been targeted.…”

COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors

“…the power supply indicator, the SRAM chip) are kept in the same operating state when the FPGA device is executing under different activation states. Under these settings, we consider that the changes in power consumption of the 9 FPGA prototyping board are mainly caused by the FPGA chip. Using the Keithley SourceMeter, we fix the input voltage to the FPGA prototyping board at 6 Volts and measure the changes of input current to it.…”

“…Their software implementations are more compact and require much smaller amount of resources. Such compact designs can effectively reduce the static energy dissipation by fitting into smaller FPGA devices [9]. Most importantly, soft processors are "configurable" by allowing the customization of the instruction set and/or the attachment of customized hardware peripherals in order to speed up the calculation of some algorithms and/or to perform some auxiliary management functionalities as described in this paper.…”