Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

Kumar, T. Santosh; Tripathi, Suman Lata

doi:10.1007/s11277-020-07765-6

Cited by 23 publications

(13 citation statements)

References 21 publications

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“…Statistics affect both delay deviations. To evaluate delay variability, 2000 Monte Carlo simulations are undertaken [ 3 ].…”

Section: Resultsmentioning

confidence: 99%

“…Due to its instability, systems that use conventional SRAM like primary memory or cache have quite a longer startup time. Nonvolatile memory can assist minimize startup time and energy consumption [ 3 , 4 ]. It is possible that a CMOS Memristor-based SRAM cell would have been an efficient circuit component that would have allowed standard memory cells to sustain data despite the power being disconnected.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

et al. 2023

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

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“…Statistics affect both delay deviations. To evaluate delay variability, 2000 Monte Carlo simulations are undertaken [ 3 ].…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

et al. 2023

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“…FinFETs are vertical channel, multiple gates, low dimension, high performance FET [21][22]. FinFET has enormous potential to suppress leakage current and improve transistor drive capabilities [23][24]. FinFETs are also compatible with CMOS logic and memory design.…”

Section: Simulation Resultsmentioning

confidence: 99%

High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Arora

Tripathi²

2022

J. Phys.: Conf. Ser.

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Graphene nano ribbon field effect transistor is an emerging field of research in VLSI technology beyond 32nm. VLSI main motive is to reduce power consumption and other parameters such as delay, PDP (power delay product) to improve the efficiency. This article discusses the requirement for high-performance applications that use little power. However, employing low-power devices for high-rank applications such as microprocessors, digital signal processors, and static random-access memory (SRAM) is very challenging. In the field of memory design and logical circuit design, it is well recognised that the Decoder plays a crucial role. As part of the planned work in 22nm technology, a technique has been developed for evaluating the parameters Power delay product, Energy delay product, Power consumption, and Delay on 14T and 15T based employing 2 to 4 decoders based on MOSFET and GNRFET. So, the final proposed circuit is obtained by application of decoders with the use of GNRFET while improving the performance parameters.

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“…Here we generate a minimum or maximum voltage supply, and minimum or maximum ground voltage for increasing the speed of operation. When there is a switching among standby mode and active mode here the circuit has three levels of design such as lower SVL, upper SVL and a mixture of both lower and upper SVL [23][24].…”

Section: Proposed Self-controllable Voltage Level Technique (Svl)mentioning

confidence: 99%

Comprehensive Analysis of 7T SRAM Cell Architectures with 18nm FinFET for Low Power Bio-Medical Applications

Kumar

Tripathi

2021

Silicon

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The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM 2 , 6T SRAM is 1.079µM 2 and that of 8T SRAM is 1.28µM 2 all the results are simulated in cadence virtuoso using 18nm technology.

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Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

Cited by 23 publications

References 21 publications

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Comprehensive Analysis of 7T SRAM Cell Architectures with 18nm FinFET for Low Power Bio-Medical Applications

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