LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories

Yang, Hsin Jung; Fleming, Kermin; Adler, Michael; Emer, Joel

doi:10.1109/fccm.2014.43

Cited by 18 publications

(22 citation statements)

References 13 publications

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“…Like an operating system, LEAP provides a unified layer of abstraction on top of device-specific drivers that interface to the underlying FPGA device, on-board memory and the host system. We build a memory hierarchy including the multi-cache system using LEAP Memories [14,15]. LEAP Memories are abstractions, which build an interface to off-chip memory underneath a uniform interface.…”

Section: Related Workmentioning

confidence: 99%

“…A multi-cache system is built by instantiating multiple memories with on-chip caches. LEAP memories also provide an optional inter-cache coherency mechanism [15]. We use both types, private (for disjoint memory regions) and coherent memories (for shared memory regions).…”

Section: Related Workmentioning

confidence: 99%

“…Recent work has also explored the design space of the cache micro-architecture [15][16][17][18][19]. Matthews et al [17] explore the efficiency in terms of speed-up versus area increase of parallel coherent L1 caches with respect to size, associativity and replacement rule in an FPGA-based soft multi-core processor.…”

Section: Related Workmentioning

confidence: 99%

“…Similarly, Choi et al [18] compare different configurations of cache size, line size and associativity of shared on-chip caches, in addition to two approaches for increasing the number of access ports of the shared cache. FCache [16] and LEAP Coherent Memories [15] target the micro-architecture of coherency mechanisms for shared memory systems in FPGAs. The goal in this work is different.…”

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Custom Multicache Architectures for Heap Manipulating Programs

Winterstein

Fleming

Yang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an FPGA accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a common approach to address this problem and the optimization of the cache architecture introduces yet another complex design space. This paper presents a high-level synthesis (HLS) design aid that automatically generates parallel multi-cache systems which are tailored to the specific requirements of the application. Our program analysis identifies non-overlapping memory regions, supported by private caches, and regions which are shared by parallel units after parallelization, which are supported by coherent caches and synchronization primitives. It also decides whether the parallelization is legal with respect to data dependencies. The novelty of this work is the focus on programs using dynamically allocated, pointer-based data structures which, while common in software engineering, remain difficult to analyze and are beyond the scope of the overwhelming majority of HLS techniques to date. Secondly, we devise a high-level cache performance estimation to find a heterogeneous configuration of cache sizes that maximizes the performance of the multi-cache system subject to an on-chip memory resource constraint. We demonstrate our technique with three case studies of applications using dynamic data structures and use Xilinx Vivado HLS as an exemplary HLS tool. We show up to 15× speed-up after parallelization of the HLS implementations and the insertion of the application-specific distributed hybrid multi-cache architecture. ¶

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Custom Multicache Architectures for Heap Manipulating Programs

Winterstein

Fleming

Yang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Altera's SDK for OpenCL [18] supports lock-free programming via SC atomics [19], though the commercial nature of the tool makes it difficult to ascertain exactly how these operations are implemented. LEAP facilitates parallel memory access through its provision of memory hierarchies that potentially can be shared among Pthreads in a lock-free manner [20].…”

Section: Introductionmentioning

confidence: 99%

Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware

Ramanathan

Wickerson

Constantinides

2018

IEEE Trans. Comput.

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Abstract-Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion but via fine-grained atomic operations ('atomics'), have been shown empirically to be the fastest class of multi-threaded algorithms in the realm of conventional processors. This article explores how these algorithms can be compiled from C to reconfigurable hardware via high-level synthesis (HLS).We focus on the scheduling problem, in which software instructions are assigned to hardware clock cycles. We first show that typical HLS scheduling constraints are insufficient to implement atomics, because they permit some instruction reorderings that, though sound in a single-threaded context, demonstrably cause erroneous results when synthesising multithreaded programs. We then show that correct behaviour can be restored by imposing additional intra-thread constraints among the memory operations. In addition, we show that we can support the pipelining of loops containing atomics by injecting further inter-iteration constraints. We implement our approach on two constraint-based scheduling HLS tools: LegUp 4.0 and LegUp 5.1. We extend both tools to support two memory models that are capable of synthesising atomics correctly. The first memory model only supports sequentially consistent (SC) atomics and the second supports weakly consistent ('weak') atomics as defined by the 2011 revision of the C standard. Weak atomics necessitate fewer constraints than SC atomics, but suffice for many multithreaded algorithms. We confirm, via automatic model-checking, that we correctly implement the semantics in accordance with the C standard. A case study on a circular buffer suggests that on average circuits synthesised from programs that schedule atomics correctly can be 6x faster than an existing lock-based implementation of atomics, that weak atomics can yield a further 1.3x speedup, and that pipelining can yield a further 1.3x speedup.

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FPGAs for Software Programmers

Koch

Hannig

Ziener

2016

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LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories

Cited by 18 publications

References 13 publications

Custom Multicache Architectures for Heap Manipulating Programs

Custom Multicache Architectures for Heap Manipulating Programs

Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware

FPGAs for Software Programmers

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