Learning characteristics of transpose-form LMS adaptive filters

Jones, Douglas L.

doi:10.1109/82.199901

Cited by 24 publications

(5 citation statements)

References 9 publications

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“…The suggestion include • Delayed LMS [263,273,274] • Look-ahead transformation of the pipelined LMS [258,275,276] • Transposed form LMS filter [277] • Block transformation using FFTs [268] We have already discussed the block transform algorithms and now wish in the following to briefly review the other techniques to improve the LMS throughput. We need therefore to ensure that the coefficient of the pipelined filter still converges to the same coefficient as the adaptive filter without pipelining.…”

Section: Pipelined Lms Filtersmentioning

confidence: 99%

“…The learning characteristics of the transposed-form adaptive filter algorithms have been investigated by Jones [277], who showed that we will get a somewhat slower convergence rate when compared with the original LMS algorithm. The stability bound regarding μ also needs to be determined and is found to be smaller than for the LMS algorithm.…”

Section: Transposed Form Lms Filtermentioning

confidence: 99%

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Digital Signal Processing with Field Programmable Gate Arrays

Meyer-Baese¹

2007

Signals and Communication Technology

192

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Section: Pipelined Lms Filtersmentioning

confidence: 99%

Section: Transposed Form Lms Filtermentioning

confidence: 99%

Digital Signal Processing with Field Programmable Gate Arrays

Meyer-Baese¹

2007

Signals and Communication Technology

192

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“…The TF-LMS adaptive filter (Jones 1992) has similar convergence behaviour as the DLMS filter. An 8-tap predictor system with mD delays is given in Figure 9.18.…”

Section: High-speed Implementationmentioning

confidence: 99%

Final Statements

2008

FPGA‐Based Implementation of Signal Processing Systems

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Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The publisher is not associated with any product or vendor mentioned in this book. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Library of Congress Cataloging-in-Publication DataWood, Roger.FPGA-based implementation of complex signal processing systems / Roger Wood ... [et al.]. p. cm. Includes bibliographical references and index.

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“…The MSE performance of the transposed DFE is about 1 dB lower than that of the direct-form DFE and it has a slow acquisition time. However, the transposed DFE allows highly parallel, almost systolic architectures for the high-speed parallel implementation of adaptive filters [23]. Hence, the proposed equalizer employs the transposed DFE architecture.…”

Section: Proposed Adaptive Equalizermentioning

confidence: 99%

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Hong

Baek

Sunwoo

2009

J Sign Process Syst

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This paper presents a novel digital signal processing (DSP) unit including a new baseline wander (BLW) corrector to support fast Ethernet in twisted pair (TP) cable channels. The proposed DSP unit consists of a programmable gain amplifier (PGA), timing recovery loop, adaptive equalizer and the new BLW corrector. Unlike the existing BLW correctors, the proposed BLW corrector calculates the BLW error by subtracting the equalizer input from the slicer output. Moreover, the new BLW corrector implemented in the digital domain uses four symbols to remove the BLW instead of the two symbols used in previous works. In addition, the proposed adaptive equalizer uses 2 −7 as the optimum step size, i.e., μ. Since μ is a multiple of 2, the equalizer eliminates the need for multipliers and, thus, has a small area and consumes less power. To verify the performance of the proposed DSP unit, floating-point and fixed-point simulations using the SPW™ tool were performed. The measured BER is less than 10 −10 when the cable length is 150 m. The proposed DSP unit was modeled by Verilog-HDL and synthesized using the 0.18 μm SEC cell library. The implemented DSP unit having 128,528 gates can operate at 142.7 MHz.

show abstract

Learning characteristics of transpose-form LMS adaptive filters

Cited by 24 publications

References 9 publications

Digital Signal Processing with Field Programmable Gate Arrays

Digital Signal Processing with Field Programmable Gate Arrays

Final Statements

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

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