Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels

Jafari, Fahimeh; Lu, Zhonghai; Jantsch, Axel

doi:10.1145/2733374

Cited by 9 publications

(20 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since a considerable number of real time applications are transmitted by Variable Bit-Rate (VBR) traffics, we have proposed a methodology [4] to consider performance analysis for VBR traffic characterized by (L, p, σ, ρ) in on-chip networks employing aggregate resource management. This method achieves more accurate delay bounds.…”

Section: A Performance Evaluation Of Real-time Servicesmentioning

confidence: 99%

“…We have described this stage in elaborate detail through our previous paper [4]. For the sake of completeness, it is explained in the appendix.…”

Section: B Inter-router Escmentioning

confidence: 99%

“…To this end, based on the Network Calculus theory [1], we have presented and proved required theorems in [2] [3]. We then presented a methodology [4] to consider resource sharing scenarios and also derive end-toend Equivalent Service Curve (ESC) and LUDB by applying the proposed theorems. We assume that all traffic can be well characterized as flows and scheduled as aggregates which means multiple flows are scheduled as an aggregate flow.…”

Section: Introductionmentioning

confidence: 99%

“…For a given flow, we study the maximum interference of all other flows based on the Network Calculus. Our proposed models [4] have been defined and validated under Round Robin (RR) policy. RR policy uses the same service level for each connection while multiple service levels allow to better adapt to the application requirements by providing different bandwidth and latency guarantees.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we extend our earlier proposed methodology for RR [4] to WRR policy. We then address an optimization problem of minimizing the total delay bounds subject to the performance constraints of the applications running on the SoC.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Jafari

Jantsch

2016

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

Abstract-We propose an approach for computing the endto-end delay bound of individual variable bit-rate flows in a FIFO multiplexer with aggregate scheduling under Weighted Round Robin (WRR) policy. To this end, we use network calculus to derive per-flow end-to-end equivalent service curves employed for computing Least Upper Delay Bounds (LUDBs) of individual flows. Since real time applications are going to meet guaranteed services with lower delay bounds, we optimize weights in WRR policy to minimize LUDBs while satisfying performance constraints. We formulate two constrained delay optimization problems, namely, Minimize-Delay and Multiobjective optimization. Multi-objective optimization has both total delay bounds and their variance as minimization objectives. The proposed optimizations are solved using a genetic algorithm. A Video Object Plane Decoder (VOPD) case study exhibits 15.4% reduction of total worst-case delays and 40.3% reduction on the variance of delays when compared with round robin policy. The optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces. We conclude that an appropriate weight allocation can be a valuable instrument for delay optimization in on-chip network designs.

show abstract

Section: A Performance Evaluation Of Real-time Servicesmentioning

confidence: 99%

“…We have described this stage in elaborate detail through our previous paper [4]. For the sake of completeness, it is explained in the appendix.…”

Section: B Inter-router Escmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Jafari

Jantsch

2016

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

Network Calculus for Bounding Delays in Feedforward Networks of FIFO Queueing Systems

Scheffler

Bondorf

2021

Quantitative Evaluation of Systems

View full text Add to dashboard Cite

Graph-Based Approach for Buffer-Aware Timing Analysis of Heterogeneous Wormhole NoCs Under Bursty Traffic

Giroudot¹,

Mifdaoui²

2020

IEEE Access

View full text Add to dashboard Cite

This paper addresses the problem of worst-case timing analysis of heterogeneous wormhole NoCs, i.e., routers with different buffer sizes and transmission speeds, when consecutivepacket queuing (CPQ) occurs. The latter means that there are several consecutive packets of one flow queuing in the network. This scenario happens in the case of bursty traffic but also for non-schedulable traffic. Conducting such an analysis is known to be a challenging issue due to the sophisticated congestion patterns when enabling backpressure mechanisms. We tackle this problem through extending the applicability domain of our previous work for computing maximum delay bounds using Network Calculus, called Buffer-aware worst-case Timing Analysis (BATA). We propose a new Graph-based approach to improve the analysis of indirect blocking due to backpressure, while capturing the CPQ effect and keeping the information about dependencies between flows. Furthermore, the introduced approach improves the computation of indirect-blocking delay bounds in terms of complexity and ensures the safety of these bounds even for nonschedulable traffic. We provide further insights into the tightness and complexity issues of worst-case delay bounds yielded by the extended BATA with the Graph-based approach, denoted G-BATA. Our assessments show that the complexity has decreased by up to 100 times while offering an average tightness ratio of 71%, with reference to the basic BATA. Finally, we evaluate the yielded improvements with G-BATA for a realistic use case against a recent state-of-the-art approach. This evaluation shows the applicability of G-BATA under more general assumptions and the impact of such a feature on the tightness and computation time.

show abstract

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels

Cited by 9 publications

References 40 publications

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Network Calculus for Bounding Delays in Feedforward Networks of FIFO Queueing Systems

Graph-Based Approach for Buffer-Aware Timing Analysis of Heterogeneous Wormhole NoCs Under Bursty Traffic

Contact Info

Product

Resources

About