Legalizing a Placement with Minimum Total Movement

Brenner, Ulrich; Vygen, Jens

doi:10.1109/tcad.2004.836733

Cited by 42 publications

(31 citation statements)

References 18 publications

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“…This minimum cost flow approach has been used a lot in practice (Vygen [1998], Brenner and Vygen [2004]). Of course, when used as a heuristic for minimizing quadratic movement costs, the flow cannot be realized arbitrarily as it is better to move many cells a little rather than one cell far.…”

Section: What Is Knownmentioning

confidence: 99%

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Combinatorial Problems in Chip Design

Körte

Vygen

2008

Bolyai Society Mathematical Studies

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The design of very large scale integrated (VLSI) chips is an exciting area of applying mathematics, posing constantly new challenges.We present some important and challenging open problems in various areas of chip design. Although the problems are motivated by chip design, they are formulated mathematically; understanding and solving them does not require any knowledge of chip design. We give some partial results and argue why a full resolution of one of the problems could result in an advance of the state of the art in algorithms for chip design.

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Section: What Is Knownmentioning

confidence: 99%

“…Still Brenner and Vygen [2004] use the above minimum cost flow approach, construct an appropriate (more sophisticated) minimum cost flow instance, and solve knapsack problems to realize the flow. This paper also proposes an integer programming formulation whose LP relaxation provides reasonable lower bounds in practice.…”

Section: Extensionsmentioning

confidence: 99%

Combinatorial Problems in Chip Design

Körte

Vygen

2008

Bolyai Society Mathematical Studies

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“…is quite natural to model this problem as a minimum cost flow problem, where flow goes from supply regions with too many objects to demand regions with extra space [43]. We have refined this approach in [11] and describe this enhanced legalization algorithm, which is part of BonnPlace, in the following. It consists of three phases.…”

Section: Overall Global Placementmentioning

confidence: 99%

“…The second phase places the cells legally within each zone in the given order. When minimizing quadratic movement, this can be done optimally in linear time, as shown in [11] (see also [20] and [9]). Finally, some post-optimization heuristics (like exchanging two cells, but also much more complicated operations) are applied.…”

Section: Overall Global Placementmentioning

confidence: 99%

BonnTools: Mathematical Innovation for Layout and Timing Closure of Systems on a Chip

2007

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Abstract-The BonnTools provide innvovative solutions for layout and timing closure that are used for many of the most complex integrated circuits. During 20 years of cooperation between the University of Bonn and IBM, new mathematical foundations and algorithms have been developed for the need of new technologies and leading-edge designs. In this paper we present the main ideas for placement, routing, timing optimization, and clock tree synthesis, which are the foundation of a continuing success story.

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“…The result from global placement may not have all overlaps between cells resolved, but the spreading of cells is sufficiently uniform to allow the next step, detailed placement or legalization, which transforms the nearly-legal result of global placement to a final legalized placement with no cell overlaps, to be performed with less cost of computation. However detailed placement generally focuses on optimizations localized to small areas of the die [DJS91,KMR04] or optimization with the objective to minimize total perturbation with respect to the global placement [BV04]. Therefore in this work we focus on global placement, as the greatest optimization potential lies in this step.…”

Section: Placementmentioning

confidence: 99%

Integration of Physical Design and Sequential Optimization

Chong¹

2006

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Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. This work examines the interaction between the physical design of digital integrated circuits and sequential optimization techniques used for performance enhancement. In particular, the integration of floorplanning and placement with retiming and clock skew scheduling is explored. A theoretical result is given which addresses the computational complexity of circuit partitioning under constraints derived from sequential optimization; this motivates the need for heuristic approaches to the related placement problem. Another theoretical result provides a characterization of the feasible retimings of a sequential circuit; this result is used to motivate an effective method for floorplanning integrated with sequential optimization. Practical techniques for using sequential slack to drive standard-cell placement are shown here; experiments demonstrate significant improvement in final design performance using these methods. Another part of this work examines how the role of sequential optimization and physical design changes when the design allows for asynchronous or latency-insensitive communication between modules. A theoretical result relating to the problem of clock tree implementation for clock skew scheduling under process variation is given. Finally an experimental technique for floorplanning using nonlinear programming is demonstrated. All rights reserved.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Integration of Physical Design and Sequential

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Legalizing a Placement with Minimum Total Movement

Cited by 42 publications

References 18 publications

Combinatorial Problems in Chip Design

Combinatorial Problems in Chip Design

BonnTools: Mathematical Innovation for Layout and Timing Closure of Systems on a Chip

Integration of Physical Design and Sequential Optimization

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