“…Subsequent work [11], [15], [17], [31], [32], which studied the correlation between instruction history and errors, indi- cated that besides the currently executed instruction, only the instruction in the previous cycle affects timing errors, neglecting the influence of all the concurrently executed instructions in the pipeline. A later study [13] considers the full pipeline depth for predicting timing errors, however, it is operand agnostic, and thereby, cannot predict bit-level timing errors (i.e., the exact bit location where timing errors occur).…”