Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study

Beraha,; Walter,; Cidon,; Kolodny,

doi:10.1109/date.2010.5457033

Cited by 9 publications

(12 citation statements)

References 20 publications

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“…This is done usually by either dedicated Synchronizer library cells (typically for single bit or small set of signals) or using an ASYNC FIFO (for multiple bits and wide data-buses) [18,16]. Existing NoC topology aproaches such as [7,10,9,12] generate a network topology but do not assign clock-domains (or frequencies) to their constituent routers. This job is left to the designer to do by visual inspection and taking into consideration the clock domains of the various cores (Masters and Slaves) which are known beforehand.…”

Section: Cdc In Network On Chip Interconnectmentioning

confidence: 99%

“…While it is feasible for the designer to assign clock-domains (or frequencies) to each router in small designs, this will be increasingly harder as SoC sizes increase. For example the 4G Modem SoC presented in [10] consists of 16 Masters and 18 Slaves with between 4 and 10 routers, even the presence of 3 or 4 clock domains would leave the designer with a large set of possible router frequency assignments. More importantly by optimizing for CDC during topology generation, the tools can generate a topology that still satisfies the performance/latency requirements, optimizes for area/power but also has a lower number of CDCs.…”

Section: Cdc In Network On Chip Interconnectmentioning

confidence: 99%

“…The optimization of CDC in a NoC requires for the modeling of a CDC cost and its inclusion in the optimization function of the SA [10,9] or GA [12] algorithms of the topology generation tools. This cost can be measured as the number of CDCs itself or as a secondary objective such as number of flops needed in the fabric.…”

Section: The Router Coloring Problemmentioning

confidence: 99%

“…The application specific network topology generation problem is a variation of the generalized steiner forest problem [6], which is known to be NP hard. Researchers have usually utilized linear-programming (LP) [7,8], simulated-annealing (SA) [9,10] or heuristic optimization [11,12,13,14,15] based techniques to solve the topology generation problem. Early approaches [13,8] focused on minimizing the dual objectives of area and power by using cost functions expressed as weighted linear combinations of area and power.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Minimizing clock domain crossing in Network on Chip interconnect

Kulkarni

Gupta

Beraha

2014

Fifteenth International Symposium on Quality Electronic Design

Self Cite

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Abstract-Network-on-Chip (NoC) architectures have been widely adopted as the preferred solution to the communication challenges of System-on-Chip (SoC) design in the nanoscale regime. SoC designs often incorporate custom NoC architectures that do not conform to regular topologies. This requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. Hence automated topology generation tools optimize for mutiple objectives like power and area to synthesize a NoC topology that meets these communication constraints. Clock-Domain-Crossings (CDCs) is an important consideration in fabric design that gets ignored in existing topology tools. CDCs add to latency and area, while also increasing verification and implementation effort. In this paper we propose a method to model and optimize the clock-domain-crossings (CDC) during NoC topology generation and prove that the underlying problem is NP-hard. We present and compare multiple approaches to model the CDC cost, including a novel fast heuristic. When applied within an existing topology generation tool our approach results in a 5% − 39% reduction in flop count of the resulting interconnect while still satisfying the original communication/performance constraints.

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Section: Cdc In Network On Chip Interconnectmentioning

confidence: 99%

Section: Cdc In Network On Chip Interconnectmentioning

confidence: 99%

Section: The Router Coloring Problemmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Minimizing clock domain crossing in Network on Chip interconnect

Kulkarni

Gupta

Beraha

2014

Fifteenth International Symposium on Quality Electronic Design

Self Cite

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show abstract

“…In addition to FPGAs, complete NoC-based SoC ASICs are presented in [7,17,72] together with a post-layout evaluation. However, neither of the works evaluate the scalability and instead focus on a single design point.…”

Section: Functional Scalabilitymentioning

confidence: 99%

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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Adaptation Strategies in Multiprocessors System on Chip

Busseuil

Almeida

Ost

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Multi-processor System-on-Chips (MPSoCs) have become increasingly popular over the past decade. They permit balancing performance and flexibility, the latter being a key feature that makes possible reusing the same silicon across several product lines or even generations. This popularity makes highlight on new challenges to deal with the increasing complexity of such systems. Programmability issues, for example, are considered with a lot of attention, as those architectures allow new dimensions in design exploration. In this context, the development of adaptable mechanisms permits the optimization of the system behavior. This chapter explors three different adaptable mechanisms, and shows their benefits : frequency scaling, task migration techniques and memory organization. The modification of the frequency of each processor of a multi-core system allows fine tuning of power consumption under a varying process workload. Task migration permits balancing load among the several processors the system is made of. Our long-term vision of future embedded devices lies in adaptive systems made of thousands of processors in which tasks frequently migrate in response to the system state that is continuously monitored. Memory organization is a crucial criterion in MPSoC performance optimization, as memory access latency of remote data increases exponentially with respect to the number of cores. The computation-based programming model commonly used in single-core or few-cores based systems are no more suitable, and a transaction-based model are necessary to reach performances needs of new multimedia application.

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Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study

Cited by 9 publications

References 20 publications

Minimizing clock domain crossing in Network on Chip interconnect

Minimizing clock domain crossing in Network on Chip interconnect

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Adaptation Strategies in Multiprocessors System on Chip

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