Libra: An Automatic Design Methodology for CMOS Complex Gates

Cardoso, Maicon S.; Smaniotto, Gustavo H.; Bubolz, Andrei A. O.; Moreira, Matheus T.; Rosa, Leomar S. da; Marques, Felipe

doi:10.1109/tcsii.2018.2866231

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…On the other hand, such cells may have an increased cost in the layout as one cannot assure the presence of the same Euler Path for both pull-down and pull-up networks [21]. The layout implications of the topology are out of the scope of this paper, however, works, such as [22,23], aim to automatically generate complex gate layouts. The techniques presented in these works can find or generate Euler paths to improve the logic gate area efficiency.…”

Section: Resultsmentioning

confidence: 99%

Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

Kessler

Muñoz

Finkenauer

et al. 2021

JICS

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Recent developments in electronic design automation tools vastly reduce the design cost of supergates, enabling an alternative approach to logic synthesis. Despite many design strategies targeting the transistors network in supergates, their comparisons are often limited to metrics such as the number of transistors used or circuit total stack, lacking an in-depth electrical evaluation. This work presents an electrical comparison of three different design techniques. The study evaluates the 3,982 logic functions of the 4 input P-class, and it shows that topologies that optimize both pull-up and pull-down networks individually presented better overall electrical characteristics. The results also suggest that reducing the logic gate stack or the number of transistors does not necessarily lead to better performance. Additionally, the results show that a single network generation method can yield in a comparatively good design or in a supergate that could achieve 50% smaller propagation delay and power dissipation by another approach, pointing to a strong dependency between the effectiveness of the method and the logic function being implemented.

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Section: Resultsmentioning

confidence: 99%

Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

Kessler

Muñoz

Finkenauer

et al. 2021

JICS

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show abstract

“…This effort focuses on digital standard cell designs and their placement modelled in a 2D plain. It should be noted that complex gates have been proposed as a valuable alternative in terms of area and delay [4]. From a transistor-layer point of view, multiple design frameworks were proposed in order to achieve area efficient layouts of radiation hardened devices [5], or highly dense integrated circuits (ICs) [6].…”

Section: Related Workmentioning

confidence: 99%

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

et al. 2018

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In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

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Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability

Cardoso

Bubolz

Cortadella

et al. 2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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Libra: An Automatic Design Methodology for CMOS Complex Gates

Cited by 6 publications

References 8 publications

Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability

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