Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Park, Yongjun; Park, Jason Jong Kyu; Park, Hyunchul; Mahlke, Scott

doi:10.1109/micro.2012.17

Cited by 23 publications

(8 citation statements)

References 19 publications

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“…Some work dynamically adapts the vector length , Lee et al, 2011, Park et al, 2012, Rivoire et al, 2006. ese designs provide SIMD execution, but allow software to use the execution units independently.…”

Section: Limits To Simd Scaling 21mentioning

confidence: 99%

Single-Instruction Multiple-Data Execution

Hughes

2015

Synthesis Lectures on Computer Architecture

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Section: Limits To Simd Scaling 21mentioning

confidence: 99%

Single-Instruction Multiple-Data Execution

Hughes

2015

Synthesis Lectures on Computer Architecture

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“…In [8], an example architecture, referred to as anySP, with configurable SIMD data-path which supports wide and narrow vector-widths is proposed. In another work [16], dynamic reconfiguration of SIMD width of the architecture based on the DLP characteristic of loops is also studied. In these works, dynamic configurability enables lane resource to execute as a traditional SIMD processor, be re-purposed to behave as a clustered VLIW processor, or combinations of both.…”

Section: Related Workmentioning

confidence: 99%

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

Diken

O’Riordan²,

Jordans

et al. 2015

2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Abstract-The degree of DLP parallelism in applications is not fixed and varies due to different computational characteristics of applications. On the contrary, most of the processors today include single-width SIMD (vector) hardware to exploit DLP. However, single-width SIMD architectures may not be optimal to serve applications with varying DLP and they may cause performance and energy inefficiency. We propose the usage of VLIW processors with multiple native vector-widths to better serve applications with changing DLP. SHAVE is an example of such VLIW processor and provides hardware support for the native 32-bit and 128-bit wide vector operations. This paper researches and implements the mixed-length SIMD code generation support for SHAVE processor. More specifically, we target generating 32-bit and 128/64-bit SIMD code for the native 32-bit and 128-bit wide vector units of SHAVE processor. In this way, we improved the performance of compiler generated SIMD code by reducing the number of overhead operations and by increasing the SIMD hardware utilization. Experimental results demonstrated that our methodology implemented in the compiler improves the performance of synthetic benchmarks up to 47%.

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“…However, it does not focus on any method for exploring the heterogeneous vector widths, as we do in our work. Another work presented in [11], referred to as Libra, also focuses on the heterogeneous construction of architectures with different vector widths. It considers dynamic reconfiguration of SIMD-width of the architecture based on the DLP characteristic of loops.…”

Section: Related Workmentioning

confidence: 99%

Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths

Diken

Jordans

Corvino

et al. 2014

Microprocessors and Microsystems

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Diken, E.; Jordans, R.; Corvino, R.; Jozwiak, L.; Corporaal, H.; Chies, F.A. Published in: Microprocessors and Microsystems DOI:10.1016/j.micpro.2014.05.004Published: 01/01/2014 Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Diken, E., Jordans, R., Corvino, R., Jozwiak, L., Corporaal, H., & Chies, F. A. (2014). Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. Microprocessors and Microsystems, 38(8), 947-959. DOI: 10.1016/j.micpro.2014.05.004 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. a b s t r a c tNumerous applications in important domains, such as communication and multimedia, show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may cause a substantial energy inefficiency. Therefore, an adequate more sophisticated exploitation of DLP is highly relevant. This paper proposes the use of heterogeneous vector widths and a method to explore the heterogeneous vector widths for VLIW ASIPs. In our context, heterogeneity corresponds to the usage of two or more different vector widths in a single ASIP. After a brief explanation of the target ASIP architecture model, the paper describes the vector-width exploration method and explains the associated design au...

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Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Abstract: Abstract

Cited by 23 publications

References 19 publications

Single-Instruction Multiple-Data Execution

Single-Instruction Multiple-Data Execution

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths

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