Library-less synthesis for static CMOS combinational logic circuits

Abstract

Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield a good synthesis results over many blocks or even for an entire chip. Consequently, this approach precludes an optimal design of individual blocks which may need custom structures. In this paper we present a new transistor bvel technique that optimizes CMOS circuits both structurally and size-wise. Our technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit pe formance of our resynthesized circuits.

Intellectual property protection by watermarking combinational logic synthesis solutions

“…The targets of latest improvements in combinational logic synthesis are refined covering algorithms [Cou92,Lia97,Gol97], optimizations on networks described using black boxes [Liu97], power optimization [Nar97,Tiw96], etc. Similarly, the research activity in technology mapping has been streamlined towards library- [Gav97,Ped96] and LUT-targeted [Hua96,Con96a] algorithms.…”

DAG based library-free technology mapping

“…Boolean methods are able to overcome the structural bias [18] of the circuit being mapped, because they do not depend on the DAG structure, but only on the function being mapped. Another important point is that the associative methods to compute series transistor constraints used in [6,7,8,9,10] are monotonically increasing with the association, meaning the association of two functions will always have more transistors in series. The Boolean method is non monotonic, meaning the association of two functions can reduce the number of transistors in series.…”

“…Unfortunately, the use of such approaches was not widely verified in a commercial level, even if other references suggest that the increased number of cells in a library could lead to significant improvements in the quality of the final design [7][8][9][10]. A recent approach presented in [11] suggests that the addition of some custom cells to a library can improve the speed of the final circuit.…”

An integrated algorithm for combined placement and libraryless technology mapping

“…A more complete exploration of the available design space can be made possible by the use of a wider range of possible gates, including complex static gates, which necessitates the use of dynamically generated libraries. The maturation of module generation techniques in layout synthesis has made the use of dynamic libraries more feasible, and their use in an industrial setting has been published in [3].…”

“…One approach performs technology mapping based on the estimated placement information [1,2,8], possibly even modeling the effects of incremental updates to the placement without actually reperforming the placement [8]; we refer to this kind of method as placement-based mapping. Another trend is to perform logic resynthesis based on the placement information [3,5,10,12]; this kind of method is called remapping. Our work differs from these in that we more completely merge the technology mapping and placement procedures by performing logic optimization considering the placement information.…”