Library Optimization for Near-Threshold Voltage Design

Hyun, Daijoon; Seo, Jung Hun; Shin, Youngsoo

doi:10.1109/iscas.2018.8351311

Cited by 2 publications

(1 citation statement)

References 7 publications

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“…The logical effort approaches [3][4] were introduced for sub-VT transistor sizing and critical path optimization. In addition, several effects were leveraged to improve the performance of cells in ULV circuits, including inverse narrow width effect (INWE) [5][6][7], reverse short channel effect (RSCE) [8][9][10], and body biasing [11][12]. Jun et al [13] reported a near-VT cell library which utilized INWE, RSCE, and forward body biasing (FBB) techniques, and demonstrated better power-delay-product (PDP) as well as energy-delay-product (EDP) in circuits design over conventional libraries.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits

Zhang

Sun

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Commercial multi-threshold standard logic cell libraries are designed for nominal super-threshold circuits. If blindly used at near-and sub-threshold voltages, such libraries exhibit excessively coarse granularity in driving strength, leading to sub-optimal logic synthesis and placement-androuting results. To tackle this problem, a holistic methodology for designing a near-and sub-threshold standard cell library that has fine driving strength granularity is presented in this paper. Meanwhile, the proposed methodology leverages inverse narrow width effect, reverse short channel effect and forward body biasing to modulate the driving strength at low area overheads. Based on the proposed methodology, we develop a 65nm multi-threshold-voltage, multi-channel-length library and benchmark it against the commercial library across several common circuits. The results show a 26.6% reduction in power-delay product, a 28.1% reduction in energy-delay product, and a 27.0% reduction in leakage power at 5.8% area overhead on average, confirming the efficiency of the methodology in near-and sub-threshold digital circuits design.

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