Lifetime reliability of thin-film SOI nMOSFET's

Wang-Ratkovic, J.; Huang, W.M.; Hwang, Bor-Yuan; Racanelli, M.; Foerstner, J.; Woo, J.C.S.

doi:10.1109/55.406797

Cited by 13 publications

(4 citation statements)

References 11 publications

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“…5,8,9) In addition, the majority of reports have defined a 10% degradation of the maximum field effect mobility as the standard lifetime of MOSFETs. 6,8,10) When conducting an accelerated experiment, the lifetime is typically extracted for a gate stress of V gs ¼ V ds =2, which is known as the worst-case condition for bulk n-type MOSFETs, however, for SOI structures, the worst case gate stress is V gs ¼ V th . 10) We evaluated the electrical characteristics of both six-step PCT devices.…”

Section: Resultsmentioning

confidence: 99%

“…6,8,10) When conducting an accelerated experiment, the lifetime is typically extracted for a gate stress of V gs ¼ V ds =2, which is known as the worst-case condition for bulk n-type MOSFETs, however, for SOI structures, the worst case gate stress is V gs ¼ V th . 10) We evaluated the electrical characteristics of both six-step PCT devices. The measured initial charge transfer characteristics of types A and B are shown in Figs.…”

Section: Resultsmentioning

confidence: 99%

“…In general, if n is in the range of 0.5-0.7, the dominant degradation mechanism is the generation of an interface state between the Si/SiO x layers due to Si-H or Si-O bond breakage caused by the energy released during the injection and recombination of electrons and holes. 10,11) Such an interface state is commonly related to an effective, negative oxide charge, controlled by the generation of acceptor-type interface states. 12,13) On the other hand, when n is in the range of 0.1-0.3, electron accumulation is enhanced to the acceptor-like state of the interface, which raises the energy barrier.…”

Section: Ds | (A)mentioning

confidence: 99%

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Electrical Characteristics of Low-Temperature Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Thin-Film Transistors with Six-Step Photomask Structure

Lee

Park²,

Oh³

et al. 2011

Jpn. J. Appl. Phys.

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We propose two types of six-step photomask, complementary metal–oxide–semiconductor (CMOS), thin-film transistor (TFT) PCT device structures in order to simplify their fabrication process compared with that of conventional, low-temperature, polycrystalline silicon (LTPS) CMOS TFT devices. The initial charge transfer characteristics of both types of six-step PCT are equivalent to those of the conventional nine-step PCT. Both types of six-step PCT are comparable to the conventional nine-step mask lightly doped drain (LDD) device in terms of the dc device lifetime of over 10 years at V ds=5 V for line inversion driving, which is the normally recognized duration time for semiconducting devices.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Ds | (A)mentioning

confidence: 99%

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Electrical Characteristics of Low-Temperature Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Thin-Film Transistors with Six-Step Photomask Structure

Lee

Park²,

Oh³

et al. 2011

Jpn. J. Appl. Phys.

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show abstract

“…However, higher-performance devices can hardly maintain good reliability, which usually embarrass device engineers. In poly-Si TFTs, devices can degrade by self-heating effect as well as hot carrier effect because of their floating body structure [2]- [3]. Although many works have been done for understanding of poly-Si device degradation phenomena, only a few studies have been reported on the degradation of both n-type TFT and p-type one made with CMOS process.…”

Section: Introductionmentioning

confidence: 99%