In the fabrication of CMOS AMLCD panel, there has been much effort to reduce the number of mask steps in order to achieve the simpler process as well as the low-cost production. In this paper, two methods for mask reduction; storage mask and LDD mask as well as self-aligned sub micron LDD n-channel TFT are introduced with good uniformity concept.

DC stress induced degradation was compared between LTPS short channel LDD NMOSFETs and PMOSFETs with a dimension of W/L = 3/3 ㎛ ㎛ ㎛ ㎛/㎛ ㎛ ㎛ ㎛ by degradation mapping of deviceparameters. Asymmetric degradation phenomena were classified for different type of devices and compared with respect to applied bias and power.