Light-PREM: Automated software refactoring for predictable execution on COTS embedded systems

Mancuso, Renato; Dudko, Roman; Caccamo, Marco

doi:10.1109/rtcsa.2014.6910515

Cited by 13 publications

(10 citation statements)

References 27 publications

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“…Such restrictions are in line with those typically imposed by state-of-the-art tools for static timing analysis. An automatic tool for code refactoring is presented in [26], making the adoption of the M/C model transparent to the programmer. Alternatively, M/C-compliant code may be written using programming models commonly adopted for heterogeneous computing systems (e.g., OpenCL 2 , OpenMP 3 , etc.)…”

Section: Related Workmentioning

confidence: 99%

Memory-processor co-scheduling in fixed priority systems

Melani

Bertogna

Bonifaci

et al. 2015

Proceedings of the 23rd International Conference on Real Time and Networks Systems

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A major obstacle towards the adoption of multi-core platforms for real-time systems is given by the difficulties in characterizing the interference due to memory contention. The simple fact that multiple cores may simultaneously access shared memory and communication resources introduces a significant pessimism in the timing and schedulability analysis. To counter this problem, predictable execution models have been proposed splitting task executions into two consecutive phases: a memory phase in which the required instruction and data are pre-fetched to local memory (M-phase), and an execution phase in which the task is executed with no memory contention (C-phase). Decoupling memory and execution phases not only simplifies the timing analysis, but it also allows a more efficient (and predictable) pipelining of memory and execution phases through proper co-scheduling algorithms. In this paper, we take a further step towards the design of smart co-scheduling algorithms for sporadic real-time tasks complying with the M/C (memory-computation) model. We provide a theoretical framework that aims at tightly characterizing the schedulability improvement obtainable with the adopted M/C task model on a single-core systems. We identify a tight critical instant for M/C tasks scheduled with fixed priority, providing an exact response-time analysis with pseudo-polynomial complexity. We show in our experiments that a significant schedulability improvement may be obtained with respect to classic execution models, placing an important building block towards the design of more efficient partitioned multi-core systems. © 2015 ACM

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Section: Related Workmentioning

confidence: 99%

Memory-processor co-scheduling in fixed priority systems

Melani

Bertogna

Bonifaci

et al. 2015

Proceedings of the 23rd International Conference on Real Time and Networks Systems

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“…One problem with the multi-phase model is that developers must manually port the existing code as a multi-phase task. To solve this problem, tools have been studied for analyzing code and converting it for multi-phase models [42,43]. In particular, there is a study that proposes a C-language-based tool to eliminate compiler dependence in code generation [42].…”

Section: Related Workmentioning

confidence: 99%

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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“…Therefore, solutions have been proposed to automate this conversion. Light-PREM [16] is a software refactoring approach to produce PREM-compliant code from legacy code, based on memory profiling tools. In [26], authors proposed a compilation technique that produces code that executes memory access phases in parallel with computation phases.…”

Section: Related Workmentioning

confidence: 99%

Code generation for multi-phase tasks on a multi-core distributed memory platform

Fort¹,

Forget²

2019

2019 IEEE 25th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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To cite this version:Frédéric Fort, Julien Forget. Code generation for multi-phase tasks on a multi-core distributed memory platform. AbstractEnsuring temporal predictability of real-time systems on a multi-core platform is difficult, mainly due to hard to predict delays related to shared access to the main memory. Task models where computation phases and communication phases are separated (such as the PRedictable Execution Model [23]), have been proposed to both mitigate these delays and make them easier to analyze.In this paper we present a compilation process, part of the Prelude compiler [20], that automatically translates a high-level synchronous dataflow system specification into a PREM-compliant C program. By automating the production of the PREM-compliant C code, low-level implementation concerns related to task communications become the responsibility of the compiler, which saves tedious and error-prone development efforts.

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Light-PREM: Automated software refactoring for predictable execution on COTS embedded systems

Cited by 13 publications

References 27 publications

Memory-processor co-scheduling in fixed priority systems

Memory-processor co-scheduling in fixed priority systems

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

Code generation for multi-phase tasks on a multi-core distributed memory platform

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