Lightweight Side Channel Resistance: Threshold Implementations of S&lt;sc&gt;imon&lt;/sc&gt;

Shahverdi, Aria; Taha, Mostafa; Eisenbarth, Thomas

doi:10.1109/tc.2016.2614504

Cited by 33 publications

(29 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Simon TI algorithm with two shares does not meet the TI requirements for hardware implementations, but is said to be suited for software implementations if an order process can be forced [23]. In our C implementation, we introduced parenthesis to specify the requested computation order.…”

Section: Resultsmentioning

confidence: 99%

“…A common evaluation approach is to perform a practical side-channel attack on selected program points considering a leakage model [23,5,7]. However, this technique is laborious and cannot cover the entire code as it is time consuming.…”

Section: Related Workmentioning

confidence: 99%

“…It relies on the trace leakage detection tests as well to find vulnerabilities related to a specific AVR microcontroller architecture. Once leakage traces are available, leakage detection using the Welsh t-test is often used to analyse the side channel resistance of protected implementations [23,7,1,18]. These leakage detection tests aim to detect the influence of secret variables on measured side channel traces using statistical hypothesis [14].…”

Section: Related Workmentioning

confidence: 99%

“…Introduced in 2013 [4], it is a family of lightweight block ciphers optimized for hardware implementations that offers a trade off between size and security level for constrained hardware and software environments. We implemented a masked version of this block cipher as explained in [23] which is based on the Threshold Implementation (TI) protection with two shares. All benchmarks implementations were done in C and compiled to the targeted ARM assembly with GCC and the optimisation level -O2, commonly used for combined performance and size optimisations.…”

Section: Enumeration Techniquesmentioning

confidence: 99%

“…The effectiveness of added countermeasures can be validated experimentally [23,7,1,18,14]. However, this approach requires specific equipment for acquiring side channel traces, which can be time consuming and error prone.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes

Ouahma¹,

Meunier²,

Heydemann³

et al.

EPiC Series in Computing

View full text Add to dashboard Cite

Masking is a popular countermeasure against side-channel attacks, which randomizes secret data with random and uniform variables called masks. At software level, masking is usually added in the source code and its effectiveness needs to be verified. In this paper, we propose a symbolic method to verify side-channel robustness of masked programs. The analysis is performed at the assembly level since compilation and optimisations may alter the added protections. Our proposed method aims to verify that intermediate computations are statistically independent from secret variables using defined distribution inference rules. We verify the first round of a masked AES in 22s and show that some secure algorithms or source codes are not leakage-free in their assembly implementations.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Enumeration Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes

Ouahma¹,

Meunier²,

Heydemann³

et al.

EPiC Series in Computing

View full text Add to dashboard Cite

show abstract

IoT Security, Privacy, Challenges, and Solutions

Garg¹,

Gambhir²,

Goel³

2022

Trust‐Based Communication Systems for Internet of Things Applications

View full text Add to dashboard Cite

Logic minimization and wide fan‐in issues in DPL‐based cryptocircuits against power analysis attacks

Tena-Sánchez

Acosta

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This paper discusses the use of logic minimization techniques and wide fan‐in primitives and how the design and evaluation of combinational blocks for full‐custom dual‐precharge‐logic‐based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate‐level design of substitution boxes, widely used in block ciphers, using sense‐amplifier–based logic in a 90‐nm technology. The security of several proposals was evaluated with simulation‐based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security‐power‐delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power‐efficient.

show abstract

Lightweight Side Channel Resistance: Threshold Implementations of S<sc>imon</sc>

Cited by 33 publications

References 18 publications

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes

IoT Security, Privacy, Challenges, and Solutions

Logic minimization and wide fan‐in issues in DPL‐based cryptocircuits against power analysis attacks

Contact Info

Product

Resources

About