Limits of instruction-level parallelism

Wall, David

doi:10.1145/106972.106991

Cited by 408 publications

(117 citation statements)

References 20 publications

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“…Until new technologies will emerge to address the power wall, the memory wall and the ILP wall [88, 177,181], CMPs are the architecture of choice in all fields of ICT. With CMPs becoming ubiquitous, parallel programming becomes a mandatory skill in order to fully exploit such architectures.…”

Section: Discussionmentioning

confidence: 99%

“…Studies showed that high parallelism can only be extracted at very high hardware costs [177]. In the beginning of the 21st century common techniques for exploiting ILP became insufficient and it was said that single-core design has hit the ILP wall.…”

Section: The Ilp Wallmentioning

confidence: 99%

“…All of them were foreseen [88, 177,181] and various architectural solutions were put forward, many of which described a CMP design. As early as 1996 Olukotun et al made their case for the development of single-chip multiprocessors [144].…”

Section: Evolution Of Cmpsmentioning

confidence: 99%

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Tuning the victim selection policy of Intel TBB

Iordan

Jahre

Natvig

2015

Journal of Systems Architecture

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In the early 2000s, the superscalar CPU paradigm reached the point of diminishing returns mainly due to power requirements and overheating concerns. Faced with a constant demand for performance, hardware developers were in need of new ways to efficiently use the ever increasing transistor count predicted by Moore's law. The Chip MultiProcessors (CMPs) came as a natural solution to the power wall: several less complex and significantly less "power hungry" cores integrated on a single chip. In almost all ICT segments today, from High Performance Computing (HPC) to embedded devices, CMPs have become the architecture of choice. With this wide adoption of CMPs, software developers need to use parallel programming to fully exploit this architecture. Although parallelization can maximize the performance and energy efficiency of applications running on CMPs, it also comes with its own set of challenges. Among these, inherent management overheads that can account for sub-linear speedups and can increase the energy consumption of executions. Because of rising concerns for energy cost and battery life, much research and development today focuses on reducing power requirements and saving energy.In this thesis, we investigate how parallel programming can be used to improve the energy efficiency of applications running on CMP systems. We focus on a programming paradigm called Task Based Programming (TBP). The base concept of the TBP model is that the programmer focuses on identifying and annotating pieces of code (tasks) which can be executed concurrently with other tasks. An important result of our work is an increased understanding of how computations, parallelization and energy consumption relate when executing on CMP systems.Working in this direction, we use a simulation framework to allow for increased flexibility in design space exploration and noninvasive measurements. Unfortunately, the performance overhead of simulation is significant: simulating a parallel application can be 10000x slower than executing it on real hardware. In the first part of our research, we took it upon ourselves to try to solve this issue. We investigate the challenges of employing a sampling based technique to take advantage of the periodic behavior in TBP parallel applications. Our proposal is a simple 3-phase methodology that identifies only a small number of representative execution samples to simulate thus reducing the overall simulation time.In the second part of our work, we look at parallelization as a mean to save energy on CMP platforms. We test and compare two TBP libraries, Wool and Intel TBB, focusing on the behavior of some basic TBP parallelization operations like task spawning, task synchronization and task stealing. We investigate the energy footprint of these parallelization overheads and the effect it has on the energy-efficiency of the executing system. We have identified that failed task steals amount for the largest overhead. To reduce their impact and improve our system's energy efficiency, we devised a new occupa...

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Section: Discussionmentioning

confidence: 99%

Section: The Ilp Wallmentioning

confidence: 99%

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Tuning the victim selection policy of Intel TBB

Iordan

Jahre

Natvig

2015

Journal of Systems Architecture

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“…Due to the fact that confidence estimators [7,8] are able to assess the quality of conditional branch predictions, they have been adopted as building blocks in many applications [17][18][19][20][21]. Confidence estimators are very similar to branch predictors [22][23][24] in the sense that they have to make binary decisions (high-confidence and low-confidence or predicted-taken and predicted-untaken, respectively). Just like branch predictors, confidence estimators have a table of Miss Distance Counters (MDCs) to keep a historical record.…”

Section: Controlling Speculative Executionmentioning

confidence: 99%

“…We use two types of branch predictors [22,31]. One is a gshare branch predictor with 2048 entries and the other is a hybrid predictor that consists of the same gshare predictor and a 2048-entry bimodal predictor.…”

Section: Simulation Environmentmentioning

confidence: 99%

The Impact of Speculative Execution on SMT Processors

Kang

Liu

Gaudiot

2007

Int J Parallel Prog

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By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are fetched from multiple threads. However, due to incorrect control speculations, a significant number of these in-flight instructions are discarded from the pipelines of SMT processors (which is a direct consequence of these pipelines getting wider and deeper). Although increasing the accuracy of branch predictors may reduce the number of instructions so discarded from the pipelines, the prediction accuracy cannot be easily scaled up since aggressive branch prediction schemes strongly depend on the particular predictability inherently to the application programs. In this paper, we present an efficient thread scheduling mechanism for SMT processors, called SAFE-T (Speculation-Aware Front-End Throttling): it is easy to implement and allows an SMT processor to selectively perform speculative execution of threads according to the confidence level on branch predictions, hence preventing wrong-path instructions 123 362 Int J Parallel Prog (2008) 36:361-385 from being fetched. SAFE-T provides an average reduction of 57.9% in the number of discarded instructions and improves the instructions per cycle (IPC) performance by 14.7% on average over the ICOUNT policy across the multi-programmed workloads we simulate.

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Building a retargetable local instruction scheduler

Allan

Beaty

et al. 1998

Softw: Pract. Exper.

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SUMMARYWhile high-performance architectures have included some Instruction-Level Parallelism (ILP) for at least 25 years, recent computer designs have exploited ILP to a significant degree. Although a local scheduler is not sufficient for generation of excellent ILP code, it is necessary as many global scheduling and software pipelining techniques rely on a local scheduler. Global scheduling techniques are well-documented, yet practical discussions of local schedulers are notable in their absence. This paper strives to remedy that disparity by describing a list scheduling framework and several important practical details that, taken together, allow implementation of an efficient local instruction scheduler that is easily retargetable for ILP architectures.The foundation of our machine-independent instruction scheduler is a timing model that allows easy retargetability to a wide range of architectures. In addition to describing how a general listscheduler can be implemented within the framework of our timing model, experimental results indicate that lookahead scheduling can profoundly improve a scheduler's ability to produce a legal schedule. Further experimental data shows that deciding to schedule a data dependence DAG (DDD) in forward or reverse order depends significantly upon that target architecture, suggesting the possibility of scheduling in each direction and using the best of the two schedules.In contrast, experiments demonstrate little difference in code quality for schedules generated by either instruction-driven or operation-driven schedulers. Thus, the inherent flexibility of operationdriven methods suggests including that approach in a retargetable instruction scheduler.List scheduling is, of course, a heuristic scheduling method. A variety of scheduling heuristics are presented. In addition, the paper describes a method, using a genetic algorithm search, to 'fine-tune' the weights of twenty-four individual heuristics to form a DDD-node heuristic tuned to a specific architecture.

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Limits of instruction-level parallelism

Cited by 408 publications

References 20 publications

Tuning the victim selection policy of Intel TBB

Tuning the victim selection policy of Intel TBB

The Impact of Speculative Execution on SMT Processors

Building a retargetable local instruction scheduler

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