Building a retargetable local instruction scheduler

Abstract

SUMMARYWhile high-performance architectures have included some Instruction-Level Parallelism (ILP) for at least 25 years, recent computer designs have exploited ILP to a significant degree. Although a local scheduler is not sufficient for generation of excellent ILP code, it is necessary as many global scheduling and software pipelining techniques rely on a local scheduler. Global scheduling techniques are well-documented, yet practical discussions of local schedulers are notable in their absence. This paper strives to remedy that disparity by describing a list scheduling framework and several important practical details that, taken together, allow implementation of an efficient local instruction scheduler that is easily retargetable for ILP architectures.The foundation of our machine-independent instruction scheduler is a timing model that allows easy retargetability to a wide range of architectures. In addition to describing how a general listscheduler can be implemented within the framework of our timing model, experimental results indicate that lookahead scheduling can profoundly improve a scheduler's ability to produce a legal schedule. Further experimental data shows that deciding to schedule a data dependence DAG (DDD) in forward or reverse order depends significantly upon that target architecture, suggesting the possibility of scheduling in each direction and using the best of the two schedules.In contrast, experiments demonstrate little difference in code quality for schedules generated by either instruction-driven or operation-driven schedulers. Thus, the inherent flexibility of operationdriven methods suggests including that approach in a retargetable instruction scheduler.List scheduling is, of course, a heuristic scheduling method. A variety of scheduling heuristics are presented. In addition, the paper describes a method, using a genetic algorithm search, to 'fine-tune' the weights of twenty-four individual heuristics to form a DDD-node heuristic tuned to a specific architecture.

Automatic data partitioning for the agere payload plus network processor

“…In cases where a successor of an instruction has a maximum time, we choose an instruction slot such that the successor with the max time has an available instruction slot within the fixed limit. This instruction is then given the highest priority in the next iteration of scheduling [2].…”

“…This forces each operation to execute within one cycle of its predecessor. Lookahead scheduling [2] ensures that all operations in the chain can be scheduled in successive slots before a choice is made. This reduces the occurrence of scheduling failure when real-time constraints are enforced.…”

Scheduling time-constrained instructions on pipelined processors

“…Other extensions and improvements have been made to foresight scheduling [Wijaya and Allan 1989;Allan et al 1998;Beaty 1992;. These algorithms all keep track of some measure of how flexible the unscheduled instructions are during the list scheduling phase and use these to dynamically reprioritize the set of ready instructions.…”