Probabilistic arithmetic, where the i th output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficient, embedded computing. Specifically, probabilistic adders and multipliers, realized using elements such as gates that are in turn probabilistic, are shown to form a natural basis for primitives in the signal processing (dsp) domain. In this paper, we show that probabilistic arithmetic can be used to compute the fft in an extremely energy-efficient manner, yielding energy savings of over 5.6X in the context of the widely used synthetic aperture radar (sar) application [1]. Our results are derived using novel probabilistic cmos (pcmos) technology, characterized and applied in the past to realize ultra-efficient architectures for probabilistic applications [2,3,4]. When applied to the dsp domain, the resulting error in the output of a probabilistic arithmetic primitive, such as an adder for example, manifests as degradation in the signal-to-noise ratio (snr) of the sar image that is reconstructed through the fft algorithm. In return for this degradation that is enabled by our probabilistic arithmetic primitives -degradation visually indistinguishable from an image reconstructed using conventional deterministic approaches -significant energy savings and performance gains are shown to be possible per unit of snr degradation. These savings stem from a novel method of voltage scaling, which we refer to as biased voltage scaling (or bivos), that is the major technical innovation on which our probabilistic designs are based.

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Inexact Circuits or circuits in which the accuracy of the output can be traded for energy or delay savings, have been receiving increasing attention of late due to invariable inaccuracies in designs as Moore's law approaches the low nanometer range, and a concomitant growing desire for ultra low energy systems. In this paper, we present a novel designlevel technique called probabilistic pruning to realize inexact circuits. Unlike the previous techniques in literature which relied mostly on some form of scaling of operational parameters such as the supply voltage (V dd ) to achieve energy and accuracy tradeoffs, our technique uses pruning of portions of circuits having a lower probability of being active, as the basis for performing architectural modifications resulting in significant savings in energy, delay and area. Our approach yields more savings when compared to any of the conventional voltage scaling schemes, for similar error values. Extensive simulations using this pruning technique in a novel logic synthesis based CAD framework on various architectures of 64-bit adders demonstrate that normalized gains as great as 2X-7.5X in the Energy-DelayArea product can be obtained, with a relative error percentage as low as 10 −6 % up to 10%, when compared to corresponding conventionally correct designs.