Limits on Adc Power Dissipation

Murmann, Boris

doi:10.1007/1-4020-3885-2_16

Cited by 91 publications

(112 citation statements)

References 16 publications

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“…Here ΔVMAX is the maximum signal change on the sampling capacitor CS and N is the number of time constants (assuming 1 for slewing and SNR/9 for linear settling) required for ½ LSB settling at the end of tracking period TTRACK. TTRACK is typically 10-20% of the clock period, 1/fS [8,11]. As shown in Table 1, IDR,MIN is typically orders of magnitude higher than the ADC supply current for the respective ADCs.…”

Section: IImentioning

confidence: 99%

“…As shown in Table 1, IDR,MIN is typically orders of magnitude higher than the ADC supply current for the respective ADCs. For a driver operating at a supply voltage, VDD and considering a track period of 10% of the clock cycle, the minimum (theoretical) required input drive power for an ideal Class A driver PIN,MIN = VDD·IDR,MIN [5,6,8] for state-of-the-art FoMw ADCs is also shown in Table 1. It can be concluded that the actual bottleneck for low power data acquisition systems lies in driving CS which is not represented by FoMW.…”

Section: IImentioning

confidence: 99%

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Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

Bindra

Lechevallier

Annema

et al. 2017

2017 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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Abstract-A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50µW for our RPS based ADC whereas it is 130µW for the conventional sampling, both much larger than the ADC power consumption of 3.25µW at 1MS/s operation. . In data acquisition systems targeted for low power wireless sensor nodes in IoTs, peripherals for microcontroller units (MCUs), the energy consumption of the associated signal processing and the analog front end circuitry to drive the ADC inputs can be much higher than the ADC power consumption. More importantly, for these IoT applications, the analog front end driving the ADC has to be always ON to present the signal to the ADC for conversion and further processing without significant latency or loss of critical information in case of any event detection. This calls for a greater attention to be paid to minimize the input drive energy of an ADC [10]. The goal of this work is to present a Range Pre-selection Sampling (RPS) based SAR ADC which helps to reduce the amount of energy required to drive the ADC inputs, so that the combined energy per conversion of driver plus the ADC is reduced.

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Section: IImentioning

confidence: 99%

Section: IImentioning

confidence: 99%

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

Bindra

Lechevallier

Annema

et al. 2017

2017 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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“…Due to the analog-centric implementation, the configurability can be exploited further towards efficient run-time power -accuracy scalability. As studied extensively by Vittoz [27], Sarpeshkar [28] and others [29], analog power consumption shows a much more pronounced dependency on the required signal to noise ratio (SNR) compared to digital power consumption, which is only logarithmically dependent on SNR requirements. As a result, dynamic accuracy scalability, which is not very effective in the digital domain, does offer opportunities in analog analytics (See 4 th INSET).…”

Section: Power-performance Scalability Though Flexible Analog Analmentioning

confidence: 99%

Where Analog Meets Digital: Analog?to?Information Conversion and Beyond

Verhelst

Bahai

2015

IEEE Solid-State Circuits Mag.

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Energy efficiency, long battery life and low latency are some of the key attributes of many emerging ultralow power sensing and monitoring systems. Applications such as always-on reactive sensor systems for natural human-device interfaces and IoT for consumer and industrial applications require ultra-low power designs beyond the promises of state of the art data converters.These devices demand for a new approach to analog-digital system partitioning with the goal of significant overall reduction in energy consumption. Many IoT applications, unlike most multimedia systems, require signal information extraction or signature extraction, rather than full reconstruction of the original sensed waveforms. Under these conditions, Nyquist rate sampling may no longer offer the optimal digitization scheme. Recent work on alternative sensor digitization strategies target drastic sampling rate reduction in the ADC, while preserving the valuable relevant information (knowledge) present in the sensed signal. This paper aims to give an overview of this emerging field of analog-to-information conversion in light of various sub-Nyquist sampling techniques recently appearing in literature, as well as highlight new opportunities, challenges and applications emerging by such converters. I.Nyquist rate vs. Information rate: Over the last several decades, a growing number of signal processing architects have embraced intensive digital signal processing preceded by a standard analog frontend and analog-to-digital converter. This trend has been exacerbated by the exponential rate of miniaturization in silicon, growing complexity of signal processing algorithms, and more systematic digital design and technology porting compared to analog design in deep submicron technology nodes. The interface between analog and digital signals has as such generally been governed by sampling at or above the Nyquist sampling rate of the analog waveforms. The dimensionality of a bandlimited signal f(t) with a physical bandwidth W over a period of T is 2WT, indicating the number of samples sufficient for perfect digital signal reconstruction. Such sampling at the Nyquist rate of 2W ensures the integrity of the signal represented by samples which are Fourier series coefficients in a Fourier series expansion of function F(w) over fundamental interval [-W W] [1]. The original signal can subsequently be reconstructed by superimposing a set of orthogonal basis functions (sinc functions) weighted by the samples f(nT). Sampling the incoming signal at this rate hence guarantees that no information about the incoming signal is lost without taking into account any heuristic or a priori side information about the signal or its information content other than the physical bandwidth. While sampling at or above Nyquist rate offers a classic and straightforward approach, it can compromise overall power efficiency.

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“…Another approach to finding a lower bound on flash ADC power consumption is given in [28]. This assumes that the comparators operate in a Class A manner and that 1/2 LSB matching with -confidence is designed.…”

Section: A Flashmentioning

confidence: 99%

“…A lower bound on power consumption of pipeline ADCs is derived in [28] which uses the power consumption of a switched-capacitor integrator (17) as a starting point Integrator (17) where is Boltzmann's constant, is the absolute temperature, SNR is the signal-to-noise ratio, is the signal frequency, is the number of time constants required to achieve the desired settling, 1 is a multiplier for to account for excess circuit noise, quantifies the fraction of supply voltage used for signal swing and is chosen to be 2/3. 2 Reference [28] presents an algorithm to estimate the power for each stage of the pipeline ADC relative to that switched-capacitor stage, taking into consideration the minimum feature size, noise, and mismatch constraints.…”

Section: B Pipelinementioning

confidence: 99%