Line edge roughness (LER) reduction strategies for EUV self-aligned double patterning (SADP)

Liu, Eric; Lutker-Lee, Katie; Lou, Qiaowei; Chen, Yaming; Raley, Angélique; Biolsi, Peter

doi:10.1117/12.2582556

Cited by 5 publications

(7 citation statements)

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“…The device performance trends shown in Figures 6 and 7 seem to be well matched to the general trends, when considering several studies shown in [20][21][22][23][24][25]. Using this HS-BNN model, we can show how both the standard deviation and mean of the electrical characteristics vary with arbitrary LER profiles in various FinFET structures.…”

Section: Resultssupporting

confidence: 76%

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Baac

Son

et al. 2022

IEEE Access

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To design a device that is robust to process-induced random variation, this study proposes a machine-learning-based predictive model that can simulate the electrical characteristics of FinFETs with process-induced line-edge roughness. This model, i.e., a Bayesian neural network (BNN) model with horseshoe priors (Horseshoe-BNN), can significantly reduce the simulation time (as compared to the conventional technology computer-aided design (TCAD) simulation method) in a sufficiently accurate manner. Moreover, this model can perform autonomous model selection over the most compact layer size, which is necessary when the amount of data must be limited. The mean absolute percentage error for the mean and standard deviation of the drain-to-source current (I DS ) were ~0.5% and ~6%, respectively. By estimating the distribution of the current-voltage characteristics, the distributions of the other device metrics, such as off-state leakage current and threshold voltage, can be estimated as well.INDEX TERMS line edge roughness (LER), process-induced random variation, Bayesian neural network, automatic model selection.

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Section: Resultssupporting

confidence: 76%

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Baac

Son

et al. 2022

IEEE Access

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“…However, this pattern requires further improvement to the level of EUV lithography (c.f. LWR and LER of ≈1.0 and 1.71 nm), [ 31–33 ] which is widely used in semiconductor lithography. Nevertheless, we can achieve a similar level of critical dimension to that of EUV lithography more efficiently in terms of process cost and complexity.…”

Section: Resultsmentioning

confidence: 99%

Atomically Flat, 2D Edge‐Directed Self‐Assembly of Block Copolymers

et al. 2022

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Nanoscale shape engineering is an essential requirement for the practical use of 2D materials, aiming at precisely customizing optimal structures and properties. In this work, sub‐10‐nm‐scale block copolymer (BCP) self‐assembled nanopatterns finely aligned along the atomic edge of 2D flakes, including graphene, MoS2, and h‐BN, are exploited for reliable nanopatterning of 2D materials. The underlying mechanism for the alignment of the self‐assembled nanodomains is elucidated based on the wetting layer alternation of the BCP film in the presence of intermediate 2D flakes. The resultant highly aligned nanocylinder templates with remarkably low levels of line edge roughness (LER) and line‐width roughness (LWR) yield a sub‐10‐nm‐wide graphene nanoribbon (GNR) array with noticeable switching characteristics (on‐to‐off ratio up to ≈6 × 104).

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“…The results of this work identified the advantages of each integration flow from an RC and via resistance point of view. The model also included secondary effects of BEOL patterning such as line edge roughness (LER) 46 – 48 and considered the impact of EUV lithography and EUV + self-aligned double patterning (SADP) required to achieve sub-30 nm pitch. From these results, all three integration approaches were shown to be relatively equivalent.…”

Section: Logic Technologymentioning

confidence: 99%

Review of virtual wafer process modeling and metrology for advanced technology development

Hargrove

Wen

Yim

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.

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Line edge roughness (LER) reduction strategies for EUV self-aligned double patterning (SADP)

Cited by 5 publications

References 0 publications

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Atomically Flat, 2D Edge‐Directed Self‐Assembly of Block Copolymers

Review of virtual wafer process modeling and metrology for advanced technology development

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