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Extreme ultraviolet (EUV) lithography has overcome significant challenges to become an essential enabler to the logic scaling roadmap. However, it remains limited by stochastically driven defects, such as line breaks and line bridges for aggressive pitches. This is especially relevant for the back end of line, which requires the most aggressive scaling. Stochastic defects reduce device yield and may push device manufacturers to move to EUV multipatterning beyond 36 nm pitch single exposure, which is a costly option. While the lithography and patterning stack can be optimized to provide the largest process window with the lowest number of defects, process margins decrease as smaller pitches are required. Currently, for some lithography stacks, especially spin-on glass based trilayer stacks, the defect-free process window beyond 36 nm pitch is limited by line collapse. Reduction in resist thickness may mitigate pattern collapse, but it may also increase the number of line breaks—trading one killer defect for another. In this paper, we expand on an area selective deposition (ASD) process in situ of an etch chamber to selectively deposit material on the EUV photoresist prior to transferring the pattern downstream. We demonstrate mitigation of resist line notching and breaks while maintaining deposition-free open areas and clear alignment marks. Due to the inherent chemical selectivity of the deposition process as opposed to a purely aspect ratio driven deposition process, thinner resists that, with a normal etch condition would result in line breaks, can now be considered. This drives down flopover defect issues seen with thicker EUV resists and enables several underlayer systems that could otherwise not be considered. Finally, we demonstrate that defectivity levels measured by e-beam inspection post lithography and post pattern transfer and yield are both improved at 30 nm pitch when this ASD process is used.

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