Linear and Nonlinear Feature Extraction for Neural Seizure Detection

Elgammal, Mohamed A.; Elkhouly, Omar A.; Elhosary, Heba; Elsayed, Mohamed; Mohieldin, Ahmed N.; Salama, Khaled N.; Mostafa, Hassan

doi:10.1109/mwscas.2018.8624031

Cited by 11 publications

(1 citation statement)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The feature extractor is composed of three feature extraction techniques, namely, fractal dimension, Hurst exponent, and Coastline. The features selection is based on the best performing features obtained in [17]. The three features along with linear Support Vector Machine (SVM) are tested with sequential minimal optimization (SMO) training that is carried out offline.…”

Section: Methodsmentioning

confidence: 99%

Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration

et al. 2021

Self Cite

View full text Add to dashboard Cite

In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardwarecalibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.

show abstract

Section: Methodsmentioning

confidence: 99%