Linear low voltage nano-scale CMOS transconductor

Abstract

This paper presents a high linearity MOSFETonly transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-lm CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mV pp differential input. The static power consumption under 1-V power supply voltage is 183 lW. Measurement results demonstrate the agreement with theoretical analyses.

A linearized technique in an All-MOS transconductance amplifier

“…The numerical value of a ranges from 1.2 to 1.7 and the value of 1.66 is a compromise on process variation [2]. In modern nanotechnology, the drain current of an MOS transistor in the linear region is even more complex [7,13]. Nevertheless, the drain current in the linear region is still strongly correlated with ðV GS ÀV THN Þ, V DS and V 2 DS .…”