Linear microcircuit fault modeling and detection

Epstein, Benjamin R.; Miller, Steven; Czigler, M.; Gray, D. R.

doi:10.1109/vtest.1991.208133

Cited by 4 publications

(1 citation statement)

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“…But, analogue circuit simulators lack the capability to alter the topology of a circuit in its textual or stored matrix representation required for the hard fault modeling. Consequently this task has been tackled in previous work for the development of fault models [22], the fault recognition from AC and DC measurements [6] [24]. Recently it was improved for parallel execution in a workstation cluster environment [21].…”

Section: State-of-the-artmentioning

confidence: 99%

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

Sebeke¹,

Teixeira²,

Ohletz³

Proceedings the European Design and Test Conference. ED&TC 1995

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Section: State-of-the-artmentioning

confidence: 99%

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

Sebeke¹,

Teixeira²,

Ohletz³

Proceedings the European Design and Test Conference. ED&TC 1995

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Fault detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing

Epstein

Czigler

Miller

1993

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Fault Coverage Measurement For Analog Circuits

Ratazzi¹

Proceedings of the IEEE Custom Integrated Circuits Conference

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This paper describes an effort to develop a technique Introduct ionMeasurement of a test pattern's fault coverage plays an important role in the specification of complex digital microcircuits. Unfortunately, analog test engineers have not enjoyed the same benefit of being able to quantify how well a test pattern detects faults. This unfortunate fact can be attributed to the nondeterministic nature of analog signals and the inability to represent physical faults in a small number of fault classes (forexample, stuck-atfaultsrepresent a large number of physical faults in digital logic circuits). Other factors which have prohibited meaningful measurement of fault coverage in analog circuits include the effect of nominal component variations on circuit response, the lack of mature analog simulators, and the wide variety of circuit functions that exist. In most cases, the development of a thorough test pattern for even simple analog circuits is based on an ad-hoc collection of sometimes redundant tests. Test specifications are developed based on the circuit's function, without regard to the circuit's architecture. Increases in the complexity of analog microcircuits and the advent of analog application-specific integrated circuits (ASIC), are pointing to the need for being able to quantify test quality and develop test patterns which account for circuit topology.

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Linear microcircuit fault modeling and detection

Cited by 4 publications

References 1 publication

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

Fault detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing

Fault Coverage Measurement For Analog Circuits

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