Lithography oriented DfM for 65 nm and beyond

Kyoh, Suigen; Kotani, Takayuki; Kobayashi, Sachiko; Ikeuchi, Atsuhiko; Inoue, Soichi

doi:10.1117/12.656858

Cited by 7 publications

(1 citation statement)

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“…2,3) To apply a more practical and effective method of hotspot fixing at both the design stage and the manufacturing stage, we have developed an automated hotspot fixer (HSF). [4][5][6][7][8][9][10] The lithography compliance check (LCC) flow utilizing the HSF is illustrated in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

Kobayashi¹,

Kyoh²,

Kotani³

et al. 2010

Jpn. J. Appl. Phys.

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As the design rule of integrated circuits is shrinking rapidly, it is necessary to use low-k 1 lithography technologies. With low-k 1 lithography, even if aggressive optical proximity correction is adopted, many sites become marginless spots, known as “hotspots”. For this problem, hotspot fixer (HSF) in design-for-manufacturability flow has been studied. In our previous work, we indicated the feasibility of layout modification using a simple line/space sizing rule for metal layers in 65-nm-node logic devices. However, in view of the continuous design-rule shrinkage and design complication, a more flexible modification method has become necessary to fix various types of hotspots. In this work, we have developed a brute-force model-based HSF. To further reduce the processing time, the hybrid flow of rule- and model-based HSFs is studied. The feasibility of such hybrid flow is studied by applying it to the full-chip layout modification of a logic test chip.

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