LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory

Jiang, Lei; Du, Yu; Zhang, Youtao; Childers, Bruce R.; Yang, Jun

doi:10.1109/dsn.2011.5958221

Cited by 39 publications

(8 citation statements)

References 25 publications

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“…There are a number of prior studies that try to extend ECP lifetime and reduce its overhead, including SAFER [Seong et al 2010b], RePRAM [Chen et al 2012], and LLS [Jiang et al 2011]. All these designs either incur higher latency due to sequential reads or increase bandwidth demands as the number of bit failures increases.…”

Section: State-of-the-art Durable Pcmmentioning

confidence: 98%

“…LLS [Jiang et al 2011] is a line-level mapping technique that ally partitions the overall PCM space into a main space and a backup space. By mapping failed lines to the backup, LLS manages to maintain a contiguous memory space that provides easy integration with wear-leveling.…”

Section: State-of-the-art Durable Pcmmentioning

confidence: 99%

“…Soft-error tolerance is not accounted. LLS[Jiang et al 2011] Intra-line salvaging method, such as ECP which correct initial cell failures. By mapping failed lines to the backup, LLS manages to maintain a contiguous memory space that provides easy integration with wear leveling.…”

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confidence: 99%

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Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing

Asadinia

Arjomand

Azad

2015

ACM Trans. Des. Autom. Electron. Syst.

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With current memory scalability challenges, Phase-Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that results in fast wear-out of memory cells. Worse, process variation in the deep-nanometer regime increases the variation in cell lifetime, resulting in an early and sudden reduction in main memory capacity due to the wear-out of a few cells. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer poor throughput or latency. In this article, we show that one of the inefficiency sources in current schemes, even when wear-leveling algorithms are used, is the nonuniform write endurance limit incurred by process variation, that is, when some memory pages have reached their endurance limit, other pages may be far from their limit. In this line, we present a technique that aims to displace a faulty page to a healthy page. This technique, called On-Demand Page Paired PCM (OD3P, for short), when applied at page level, can improve PCM time-to-failure by 20% on average for different multithreaded and multiprogrammed workloads while also improving IPC by 14% on average compared to previous page-level techniques. The comparison between line-level OD3P and previous line-level techniques reveals about 2× improvement of lifetime and performance. ACM Reference Format:Marjan Asadinia, Mohammad Arjomand, and Hamid Sarbazi Azad. 2015. Prolonging lifetime of PCM-based main memories through on-demand page pairing.

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Section: State-of-the-art Durable Pcmmentioning

confidence: 98%

Section: State-of-the-art Durable Pcmmentioning

confidence: 99%

See 1 more Smart Citation

Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing

Asadinia

Arjomand

Azad

2015

ACM Trans. Des. Autom. Electron. Syst.

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“…SAFER [Seong et al 2010b] dynamically partitions the blocks into multiple groups, exploiting the fact that failed cells can still be read and reused to store data. LLS [Jiang et al 2011] is a line-level mapping technique that dynamically partitions the overall PCM space into a main space and a backup space. By mapping failed lines to the backup, LLS manages to maintain a contiguous memory space that provides easy integration with wear leveling.…”

Section: Pcm Based Main Memory and Wear-out Problemmentioning

confidence: 99%

Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks

Chen

Venkataramani

Huang

2014

J. Emerg. Technol. Comput. Syst.

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DRAM technology challenges have increased the necessity to adapt to the emerging memory technologies like Phase-Change Memory (PCM or PRAM). While such emerging technologies provide benefits like storage density, nonvolatility, and low energy consumption, they are constrained by limited write endurance that becomes more pronounced with process variation. In this article, we explore a novel PRAM-based main memory system which resuscitates a group of faulty pages in a cost-effective manner to significantly extend the PCM main memory lifetime while minimizing the performance impact. In particular, we explore three different dimensions of dynamic redundancy levels and group sizes, and design low-cost hardware and software support for our proposed schemes. We aim to have minimal hardware modifications (that have less than 1% on-chip and off-chip area overheads). Also, our schemes can improve the PRAM lifetime by up to 105× (times) over a chip with no error correction capabilities, and outperform prior schemes such as DRM and ECP at a small fraction of the hardware cost. The performance overhead resulting from our scheme is less than 8% on average across 21 applications from SPEC2006, Splash-2, and PARSEC benchmark suites.

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“…Specifically for the former, to reuse as many worn-out pages as possible, methods on page recycling [3], [4] are introduced. Regarding the latter perspective of data writing patterns, methods on write reduction [1,2,5,6] and wear leveling [2,[7][8][9] have been proposed. It should be noted that the methods mentioned above are independent of one another.…”

Section: Introductionmentioning

confidence: 99%

Warranty-aware page management for PCM-based embedded systems

Cheng¹,

Chang²,

Chang³

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The thriving growth in mobile consumer electronics makes energy efficiency in the embedded system design an important and recurring theme. Phase Change Memory (PCM) has shown its potential in replacing DRAM as the main memory option due to its (65%) reduced energy requirements. However, when considering the usage of PCM main memory, its write endurance becomes a critical issue, and wear leveling design is a common approach to resolve this issue. Even though the wear leveling design should stress operation efficiency and overhead reduction, existing wear leveling strategies designed for PCM main memory are usually dedicated to prolonging the lifetime of PCM. In this paper, we propose the perspective that, instead of valuing PCM lifetime exploitation as the first priority, we should turn to satisfy the product warranty period. To this end, further enhancement of operation efficiency and reduction of management overhead could be achieved. We thus propose a warrantyaware page management design to enhance the operation efficiency for managing the endurance issue in PCM. To show the effectiveness of the proposed design, we collected real traces on fiasco.OC by running SPEC2006 benchmarks with different write intensity workloads. The experiment results showed that our design reduced the overhead to one third of that of the state-of-the-art designs while still providing the same level of performance.

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LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory

Cited by 39 publications

References 25 publications

Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing

Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing

Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks

Warranty-aware page management for PCM-based embedded systems

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