Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Xiao, Linfu; Xiao, Zigang; Qian, Zaichen; Jiang, Yan; Huang, Tao; Tian, Haitong; Young, Evangeline F. Y.

doi:10.1109/iccad.2010.5653732

Cited by 31 publications

(29 citation statements)

References 9 publications

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“…Some methods to analyze the characteristics of mesh structures are proposed in [4], [27] and a combinatorial algorithm to optimize a clock mesh is proposed in [24]. An obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis is proposed in [21], [26]. A methodology based on binary linear programming for clock mesh synthesis is described in [5].…”

Section: Meshesmentioning

confidence: 99%

“…Compared to traditional tree structures, clock-network capacitance is increased by 59.5% to satisfy the difficult skew constraints with 4.5ps skew limit. Table III compares our clock network with those produced by CNSRouter [26] and by techniques in [21]. Our clock network is more robust than meshes with significantly smaller total capacitance.…”

Section: A Experiments Designmentioning

confidence: 99%

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Multilevel tree fusion for robust clock networks

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Recent improvements in clock-tree and mesh-based topologies maintain a healthy competition between the two. Trees require much smaller capacitance, but meshes are naturally robust against process variation and can accommodate late design changes. Cross-link insertion has been advocated to make trees more robust, but is limited in practice to short distances. In this work we develop a novel non-tree topology that fuses several clock trees to create large-scale redundancy in a clock network. Empirical validation shows that our novel clock-network structure incrementally enhances robustness to satisfy given variation constraints. Our implementation called Contango3.0 produces robust clock networks even for challenging skew limits, without parallel buffering used by other implementations. It also offers a fine trade-off between power and robustness, increasing the capacitance of the initial tree by less than 60%, which results in 2.3× greater power efficiency than mesh structures.

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Section: Meshesmentioning

confidence: 99%

Section: A Experiments Designmentioning

confidence: 99%

Multilevel tree fusion for robust clock networks

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…The mesh is repeatedly divided into four rooms till the sum of the capacitances of clock sinks in a room is less than a target capacitance (say 100 fF). Though a similar congestion driven method is used in [8], a complete framework including mesh buffer design and buffer placement has not been reported. The capacitance driven mesh is highly non uniform with some big rooms and very small rooms (Fig.…”

Section: Capacitance Driven Mesh Formationmentioning

confidence: 99%

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Reuben

Zackriya.V

Nashit

et al. 2013

IEICE Electron. Express

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Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skewdriven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

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“…Methods to analyze the characteristics of mesh structures are proposed in [4], [33] and a combinatorial algorithm to optimize a clock mesh is proposed in [30]. Obstacle-avoiding clock mesh synthesis in [28], [32] applies a two-stage approach -mesh construction followed by driving-tree synthesis. A clock-mesh synthesis methodology based on binary linear programming is described in [6].…”

Section: Meshes and Cross-linksmentioning

confidence: 99%

Algorithmic tuning of clock trees and derived non-tree structures

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.I. INTRODUCTION Clock-network synthesis significantly impacts the performance, area and power dissipation of an integrated circuit, and this impact is aggravated when architectural-level pipelining increases the number of clocked elements [35]. Being responsible for 30-50% of chip power [9], clock networks require careful optimization. Such optimization may require SPICEaccurate timing analysis, otherwise it is difficult to account for the explosion of technology parameters that characterize each advanced technology node. Unfortunately, runtime overhead limits such analysis to only several invocations during optimization. Recent research reviewed in this paper developed comprehensive SPICE-accurate clock-network optimizations subject to capacitance and slew constraints, and cognizant of runtime limitations. The ISPD 2009 and 2010 Clock-Network Synthesis contests organized by IBM Research and Intel Research evaluated these techniques on industry benchmarks. The second contest increased the realism in modeling and evaluation of clock networks, adding the impact of variations and using local rather than global clock skew -a more meaningful parameter for large circuits [10].The growing impact of process, voltage and temperature (PVT) variation complicates the design of reliable clock networks [26], as nominal-parameter optimizations (single corner, no variation) do not ensure high yield. Robustness to variations requires increased power and careful trade-offs. Mesh/grid structures exhibit greater robustness but consume much more power and complicate clock gating. This paper surveys recent clock-network topologies that offer the path-redundancy of meshes, but retain the advantages of clock trees.Clock networks can also be improved by careful positioning of latches and flip-flops. Leaf-level register clustering [3] after global placement can help sharing inverters between flip-flops and reduce clock-network capacitance. In this paper, we review a recent, more general optimization [17] that differentiates sequential elements during global placement and optimizes total dynamic power of signal nets and the clock network.

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Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Cited by 31 publications

References 9 publications

Multilevel tree fusion for robust clock networks

Multilevel tree fusion for robust clock networks

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Algorithmic tuning of clock trees and derived non-tree structures

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