Logarithmic Number System and Floating-Point Arithmetics on FPGA

Matousek, R.; Tichý, M.; Pohl, Z.; Kadlec, J.; Softley, C.I.; Coleman, Nick

doi:10.1007/3-540-46117-5_65

Cited by 35 publications

(17 citation statements)

References 5 publications

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“…Fully parameterizable floating point libraries [1,11] allow extensive explorations of different precisions and methods for automatic optimization of the operand sizes have been proposed [12,13]. Another option for FPGAs is to use logarithmic number systems which avoid the quadratic complexity of the multiplier but complicate the adder [18,23].…”

Section: Floating Point Numbers On Fpgasmentioning

confidence: 99%

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

Strzodka¹,

Göddeke

2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing resource usage of multipliers depending on the operand size. Many research efforts have been devoted to the optimization of individual arithmetic and linear algebra operations. In this paper we take a higher level approach and seek to reduce the intermediate computational precision on the algorithmic level by optimizing the accuracy towards the final result of an algorithm. In our case this is the accurate solution of partial differential equations (PDEs). Using the Poisson Problem as a typical PDE example we show that most intermediate operations can be computed with floats or even smaller formats and only very few operations (e.g. 1%) must be performed in double precision to obtain the same accuracy as a full double precision solver. Thus the FPGA can be configured with many parallel float rather than few resource hungry double operations. To achieve this, we adapt the general concept of mixed precision iterative refinement methods to FPGAs and develop a fully pipelined version of the Conjugate Gradient solver. We combine this solver with different iterative refinement schemes and precision combinations to obtain resource efficient mappings of the pipelined algorithm core onto the FPGA.

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Section: Floating Point Numbers On Fpgasmentioning

confidence: 99%

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

Strzodka¹,

Göddeke

2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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“…Although addition and subtraction are more complex in LNS, recent advances have made them feasible in small FPGA devices. We use the High Speed Logarithmic Arithmetic (HSLA) cores, described in [15]. Table I shows the resource requirements of our LNS units in comparison to Underwood's [16] highly-optimized IEEE single-precision floating point units.…”

Section: Logarithmic Arithmeticmentioning

confidence: 99%

“…To reduce the resource requirements of the floating-point computations, we represent numbers using the logarithmic number system (LNS) [14], [15]. To evaluate the design, a configurable 1000-1-4244-0383-9/06/$20.00 ©2006 IEEE 0) Initialization:…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic

Tichý

Schier

Gregg

2006

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

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Abstract-Adaptive filters are used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. The GSFAP algorithm, discussed in the paper, is characterized by convergence superior to the popular NLMS, with only slightly higher complexity. The paper deals with floating-point-like implementation of algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The design is crafted to make efficient use of the pipelined logarithmic addition units. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and it allows a higher signal sampling rate (around 70 kHz) for the corresponding filter orders, GSFAP has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems.

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“…The first type is the logarithmic number system arithmetics, namely the High-Speed Logarithmic Arithmetic (HSLA) library [11] implementing multiplication, division and square-root operations simply as fixed-point addition, subtraction and right shift. Addition and subtraction operations require more complicated evaluation, hence only one pipelined addition/subtraction unit is usually available for a given application.…”

Section: Introductionmentioning

confidence: 99%