Logic gates constructed on CdS nanobelt field-effect transistors with high-κ HfO2 top-gate dielectrics

Wu, Pingfan; Ye, Y.; Liu, C.; M., R.; Sun, Tao; Dai, Li‐Xin

doi:10.1039/b909595k

Cited by 18 publications

(11 citation statements)

References 26 publications

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“…The results of the inverters with other load resistances are also displayed in Figures and S9. Despite the relatively smaller voltage gains from forward sweeping, when considering that the load is a common resistor instead of carefully selected transistors that are usually utilized in other reports with high voltage gains, − the results obtained in this work demonstrate the high performance of the steep slope FETs again.…”

Section: Resultsmentioning

confidence: 74%

In₂O₃ Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

Liu

Wan

et al. 2018

ACS Nano

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Heat dissipation is a key issue for scaling metal-oxide-semiconductor field-effect transistors (MOSFETs). The Boltzmann distribution of electrons imposes a physical limit on the subthreshold swing (SS), which impedes both the reduction of the switching energy and the further increase of the device density. The negative capacitance effect is proposed to rescue MOSFETs from this phenomenon called “Boltzmann tyranny”. Herein, we report In2O3 nanowire (NW) transistors with SS values in the sub-60 mV/dec region, which utilize the ferroelectric P(VDF-TrFE) as the dielectric layer. An ultralow SS down to ∼10 mV/dec is observed and spans over 5 orders of magnitude in the drain current. Meanwhile, a high on/off ratio of more than 108 and a transconductance (g m) of 2.3 μS are obtained simultaneously at V d = 0.1 V. The results can be understood by the “voltage amplification” effect induced from the negative capacitance effect. Moreover, the steep slope FET-based inverters indicate a high voltage gain of 41.6. In addition to the NOR and NAND gates, the Schmitt trigger inverters containing only one steep slope FET are demonstrated. This work demonstrates an avenue for low-power circuit design with a steep SS.

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Section: Resultsmentioning

confidence: 74%

In₂O₃ Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

Liu

Wan

et al. 2018

ACS Nano

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“…In addition to the high on/off current ratio, the standby current ( I ds at V g = 0 V) was ∼3 × 10 –13 A (Figure e, marked by the pink dashed line), 3 orders of magnitude lower than that of planar E-mode CdS FETs (∼10 –10 A) . Low standby current is important for reducing FET power consumption. − The subthreshold swing ( S ) (Figure e) and transconductance ( g m ) (Figure f, blue) derived from the transfer characteristics at V ds = 1 V were 637 mW/dec and 0.52 μS, respectively. Therefore, the electron mobility (μ e ) and electron concentration ( n e ) of CdS nanowalls were estimated to be about 3.2 cm 2 /(V·s) and 1.1 × 10 18 cm –3 , respectively (see calculation details in the Supporting Information).…”

Section: Resultsmentioning

confidence: 99%

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

Oksenberg

Popovitz‐Biro

et al. 2017

J. Am. Chem. Soc.

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Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10, 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

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“…128 Dai and co-workers have designed and constructed a high-performance NOT logic gate (inverter), NOR, and NAND gate on CdS NWs. 62,69,129 The basic components of these devices are high-performance MESFETs made on single CdS NWs where top Schottky gates have been employed, as shown in Fig. 23.…”

Section: Logic Circuitsmentioning

confidence: 99%

One-dimensional CdS nanostructures: synthesis, properties, and applications

et al. 2010

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One-dimensional (1D) semiconductor nanostructures are of prime interest due to their potential in investigating the size and dimensionality dependence of the materials' physical properties and constructing nanoscale electronic and optoelectronic devices. Cadmium sulfide (CdS) is an important semiconductor compound of the II-VI group, and its synthesis and properties have been of growing interest owing to prominent applications in several fields. This article provides a comprehensive review of the state-of-the-art research activities that focus on the rational synthesis, novel properties and unique applications of 1D CdS nanostructures in nanotechnology. It begins with the rational design and synthesis of 1D CdS nanostructures, and then highlights a range of unique properties and applications (e.g. photoluminescence, cathodoluminescence, electrochemiluminescence, photocatalysis, lasers, waveguides, modulators, solar cells, field-effect transistors, photodetectors, field-emitters, and nanogenerators) associated with them. Finally, the review is concluded with the author outlook of the perspectives with respect to future research on 1D CdS nanostructures.

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Logic gates constructed on CdS nanobelt field-effect transistors with high-κ HfO2 top-gate dielectrics

Cited by 18 publications

References 26 publications

In₂O₃ Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

In₂O₃ Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

One-dimensional CdS nanostructures: synthesis, properties, and applications

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Logic gates constructed on CdS nanobelt field-effect transistors with high-κ HfO2 top-gate dielectrics

Cited by 18 publications

References 26 publications

In2O3 Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

In2O3 Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

One-dimensional CdS nanostructures: synthesis, properties, and applications

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Product

Resources

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In₂O₃ Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

In₂O₃ Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications