Logic-in-Memory: A Nano Magnet Logic Implementation

Abstract

In most computational systems memory access represents a relevant bottleneck for circuits performance. The execution speed of algorithms is severely limited by memory access time. An emerging technology like NanoMagnet Logic (NML), where its magnetic nature leads to an intrinsic memory ability, represents therefore a very promising opportunity to solve this issue. NanoMagnet Logic is the ideal candidate to implement the so called Logic-In-Memory (LIM) architecture. But how is it possible to organize an architecture where logic and memory are mixed and not separated entities?In this paper we try to address this issue presenting our recent developments on LIM architectures. We originally conceived a LIM architecture without considering any technological constraints. Here we present the first adaptation of that architecture to NanoMagnet Logic technology. The architecture is based on an array of identical cells developed on three virtual layers, one for logic, one for memory and one for information routing. These three virtual layers are mapped on two physical layers exploiting all our recent improvements on NanoMagnet Logic technology, which are validated with the help of low level simulations. The structure has been tested implementing two different algorithms, a sort algorithm and an image manipulation algorithm. A complete characterization in terms of area and power is reported. The structure here presented is therefore the first step of an ongoing effort directed toward the development of truly innovative architectures.

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

“…Moreover, pNML technology allows one to build 3D structures by stacking different layers of nanomagnets [44,45,46,47]. Previous works such as [42,48,49,50,51,52] already explore the potentialities of NanoMagnetic Logic architectures (3D and non), but none of them propose a complete Logic-in-Memory design, which is instead presented in the following.…”

Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing

“…Some researchers [3][4][5][6] have proposed using multiple layers to create three-dimensional NML circuits and structures. Specifically [5,6] have used the stacking of multiple layers of NML cells to create circuits. These designs utilise magnetic vias to allow signals to propagate between logic planes.…”

“…One such design [7] requires multiple copies of each input to ensure correct logic function of the circuit. A separate work [5] contains a full adder NML design that uses multiple layers to avoid the need for multiple copies of each inputs. In this Letter, we propose a five-input majority gate using multiple layers in NML.…”

“…In this Letter, we propose a five-input majority gate using multiple layers in NML. By using our proposed five-input majority gate we are able to improve on the number of cells in the full adder design from [5] without requiring additional input copies such as in [7]. We wanted our designs to consist of uniform symmetric cells so other existing designs such as [3,4,8], and so on, were not considered in our comparisons.…”

A compact physical model for the simulation of pNML-based architectures

“…This is possible by forcing one of the three inputs of the Minority Gate into a specific logic value. The concept of a programmable gate can be extended and redesigned in a 3D environment, exploiting the Logic-in-Memory (LIM) concept 5,6 by placing programmable inputs into separated layers as already. The design of logic circuits represent a key point for the study of emerging technologies.…”