Logic masking for SET Mitigation Using Approximate Logic Circuits

Abstract

Logic masking approaches for Single-Event Transient (SET) mitigation use hardware redundancy to mask the propagation of SET effects. Conventional techniques, such as Triple-Modular Redundancy (TMR), can guarantee full fault coverage, but they also introduce very large overheads. Alternatively, approximate logic circuits can provide the necessary flexibility to find an optimal balance between error coverage and overheads. In this work, we propose a new approach to build approximate logic circuits driven by testability estimations. Using the concept of unate functions, approximations are performed in lines with low testability in order to minimize the impact on error coverage. The proposed approach is scalable and can provide a variety of solutions for different trade-offs between error coverage and overheads.

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

“…The approach in [18] considers the failure probabilities of the gates and uses a two-level representation. Finally, [19] approximates a circuit by removing circuit lines with low testability. However, this method does not allow to estimate the error probability produced by the approximation transformations.…”

“…However, in approximate synthesis, the discrepancy is allowed. A preliminary approach that exploits this technique has been proposed in [19].…”

“…In [19], all lines whose fault probability is below a selected threshold are approximated. In this work we follow an iterative approach.…”

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

“…The reinforcement network, in the worst case, is a replica of the classical pull-up and pull-down, which will cover all possible situations, but usually, strengthening the output is not required for all input values but rather only for those who have no logical masking in the propagation path up to the next memory element or output [21]. Therefore, the area overhead is substantially reduced, For instance, in a NAND gate with "n" inputs, a low level output appears when "n" serial transistors are affected by a soft error.…”

“…This parameter can affect the reliability of the system, and force it to modify the clock period, i.e., a system with a refresh rate between memory elements (e.g. flip-flops, latches) of 20 Ghz, (50 ps period between samples), switching timing errors over this value will cause a soft error in nodes inside a logic sensitized path [21].…”