Logic simplification by minterm complement for error tolerant application

Ichihara, Hideyuki; Inaoka, Tomoya; Iwagaki, Tsuyoshi; Inoue, Tomoo

doi:10.1109/iccd.2015.7357089

Cited by 8 publications

(6 citation statements)

References 14 publications

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“…Other works use the name of the technique that applies these approaches. For instance, Ichihara et al, in [14], use cube expansion and cube reduction, whereas Ammes et al, in [19], adopt the terms cube insertion and cube removal. For the sake of simplicity, in this work, it is adopted the terms 0-1 and 1-0 minterm complements.…”

Section: A Backgroundmentioning

confidence: 99%

“…On the other hand, in [14], Ichihara et al propose a greed ALS method that applies both minterm complement techniques. To perform the approximation, they apply on two transformations: expansion (for 0-1 complement) and reduction (for 1-0 complement) of cubes from the given logic function.…”

Section: B Related Workmentioning

confidence: 99%

“…The 2L circuit optimization focuses on reducing the number of operations in SOP/POS expressions, whereas the multilevel optimization goal varies according to the Boolean structure addressed but aims to reduce the number of operations (i.e, the logic gate count) and the circuit logic depth. This paper presents an extensive survey about 2L [11][12][13][14][15][16][17][18][19] and multilevel ALS methods presented in the literature up to now. It is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

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Two-Level and Multilevel Approximate Logic Synthesis

Ammes

Butzen

Reis

et al. 2022

JICS

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Approximate computing represents a modern design paradigm that allows systems to have imprecise or inexact execution, aiming to optimize circuit area, performance, and power dissipation. The automatic construction of approximate integrated circuits (IC) is performed through computer-aided design (CAD) tools available in electronic design automation (EDA) frameworks. Approximate logic synthesis (ALS), in particular, treats two-level and multilevel topologies of combinational blocks in the development of digital IC design. This work provides a survey of ALS methods presented in the literature, from the pioneers until the state-of-the-art approaches.

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Section: A Backgroundmentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Two-Level and Multilevel Approximate Logic Synthesis

Ammes

Butzen

Reis

et al. 2022

JICS

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“…The logic synthesis technique for area reduction using the error rate threshold was proposed in [3]. Minimising the number of literals reduces circuit complexity through minterm/maxterm compliment based on error tolerance capability [4]. Ichihara [4] only deals with a single circuit and iteratively simplifies a given logic function through expansions/reductions of prime implicants.…”

Section: Introductionmentioning

confidence: 99%

“…Minimising the number of literals reduces circuit complexity through minterm/maxterm compliment based on error tolerance capability [4]. Ichihara [4] only deals with a single circuit and iteratively simplifies a given logic function through expansions/reductions of prime implicants. By using a specified input space that is most vulnerable to errors, approximate logic circuits provide low overhead concurrent error masking for a given logic circuit [5].…”

Section: Introductionmentioning

confidence: 99%

Input vulnerability‐aware approximate triple modular redundancy: higher fault coverage, improved search space, and reduced area overhead

et al. 2018

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Area overhead reduction in conventional triple modular redundancy (TMR) by using approximate modules has been proposed in the literature. However, the vulnerability of approximate TMR (ATMR) in the case of a critical input, where faults can lead to errors at the output, is yet to be studied. Here, identifying critical input space through automatic test pattern generation and making it unavailable for the technique of approximating modules of TMR (ATMR) were focused, which involves a prime implicant reduction expansion. The results indicate that the proposed method provides 75-98% fault coverage, which amounts up to 43.8% improvement over that achieved previously. The input vulnerability-aware approach enables a drastic reduction in search space, ranging from 41.5 to 95.5%, for the selection of candidate ATMR modules and no compromise on the area overhead reduction is noticed.

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