Logic transformation for low power synthesis

Hwang, TingTing; Liu, C.L.; Kang, Sung‐Mo

doi:10.1145/307418.307480

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…Further, fast algorithms are needed for fast design space exploration of large circuits, which could contain thousands of MUXes. The results of [6] have since been used in several related contexts [4,7].…”

Section: Introductionmentioning

confidence: 99%

Improved Algorithms for Low Power Multiplexor Decomposition

Yang¹,

Leong²

2005

J CIRCUIT SYST COMP

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It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the design of MUXes that consumes less power. This is called the low power MUX decomposition problem and has been studied in Ref. 1. This paper improves on the results of Ref. 1 in two ways: (a) we propose a method to speed up the algorithms in Ref. 1, and (b) we propose a post-optimization procedure to further reduce the overall power dissipation of decompositions obtained by any MUX decomposition algorithm. Using this post-optimization procedure, we have been able to further reduce the power dissipation results of Ref. 1.

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Section: Introductionmentioning

confidence: 99%

Improved Algorithms for Low Power Multiplexor Decomposition

Yang¹,

Leong²

2005

J CIRCUIT SYST COMP

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“…Area and delay are measured using SIS after technology mapping. Power consumed by the circuit is measured using FIT power estimation tool [6], whose accuracy of the power estimation is within 5% from HSPICE. Table 1 compares the results of inverter elimination by duplication, our implication graph (IG) based optimal algorithm and heuristic algorithm for the ISCAS-85 circuits.…”

Section: Resultsmentioning

confidence: 99%

Implication graph based domino logic synthesis

Kim

Liu

Kang

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on implication graph can reduce transistor counts by 25% and power delay product by 25% on average.

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Using negative edge triggered ffs to reduce glitching power in FPGA circuits

Czajkowski

Brown

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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This paper presents an algorithm for reducing dynamic power dissipated by Field-Programmable Gate Array (FPGA) circuits. The algorithm uses a fast probability based model to estimate glitches on wires in a circuit and then inserts negative edge triggered FFs at outputs of Lookup Tables (LUTs) that produce glitches. A negative edge triggered FF maintains the logic value produced by the LUT in the previous cycle for the first half of the clock period, filtering glitches that occur at the output of the LUT. The power dissipation is lowered by reducing the number of transitions that propagate to the general routing network.We applied the algorithm to a set of benchmark circuits implemented on a commercial FPGA, Altera's Stratix II. The results obtained using Quartus II 5.1 CAD tool show a reduction in dynamic power dissipation by 7% on average and up to 25%.

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Logic transformation for low power synthesis

Abstract: In

Cited by 3 publications

References 11 publications

Improved Algorithms for Low Power Multiplexor Decomposition

Improved Algorithms for Low Power Multiplexor Decomposition

Implication graph based domino logic synthesis

Using negative edge triggered ffs to reduce glitching power in FPGA circuits

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