Logic verification of very large circuits using Shark

Abstract

In this paper, we will present Shark, a software based logic verification technology that allows high-performance switch-level simulation of multi-million transistor circuits on general-purpose workstations. Shark achieves high-performance simulations on very large circuits through three key technologies: 1) a circuit partitioner based on latch boundary components, design hierarchy driven clustering, and latch/activity load balancing, 2) a high-performance switch-level simulator capable of simulating very large models and run word-parallel simulations, and 3) a simulation backplane that can connect any number of simulators to form a distributed/parallel simulation environment. Shark has been tested on circuits of up to 15M transistors. On an Intel circuit with about 5M transistors, Shark achieved a simulation throughput of 19Hz.

Fast co-verification of HDL models

“…In addition to the importance of the TTM, any imperfection in the verification process may lead to significant property loss, and costly redesigns. Hardware verification is the process of verifying the layout of a circuit design, as the layout is functionally equivalent to a higher level of its specification (e.g., RTL) [7]. Three main approaches are utilized in the design verification (DV) [34]: formal verification [37,29], simulation [24,5,1], and emulation [28,16].…”

Switch-level emulation

“…The switch-level is an abstraction-level, which is more accurate and detailed than gate-level models [13] and can be used in many applications such as design verification [5][10] and fault simulation [11]. However, the simulation of switch-level models is more time-consuming than gate-level models.…”

“…The parallel simulation method produces speed-ups proportional to the number of the computers in the network. In the parallel simulation method the communication cost across the network is one of the crucial limiting factors [5]. One method for accelerating the verification of digital systems is the use of FPGA-based logic emulation systems.…”