Estimating the maximum clock frequency of homogeneous Coarse Grained Reconfigurable Arrays/ Architectures (CGRAs) with an arbitrary number of Processing Elements (PE) is difficult. Clock frequency estimation of highly heterogeneous CGRAs takes additional factors into account, thus is even more difficult. Main challenges are the heterogeneous set of operators for each Processing Element (PE) and the irregular interconnect (connecting a CGRA’s PEs). Multiple estimation approaches could be reasonable. We propose an optimized statistical estimator, which is based on our prior work. We demonstrate its superiority to state of the art neural networks in terms of accuracy and robustness, especially in situations with a sparse set of training data.