Loop optimization in register-transfer scheduling for DSP-systems

Abstract

In this paper, we discuss a control-.fiow transformation called loop folding, during the scheduling of register-transfer code for DSP-systems.

A formal approach to the scheduling problem in high level synthesis

“…The idea of loop folding was proposed in [24]. The goal of loop folding is to reduce the running time of a loop by overlapping the execution of different loop iterations.…”

“…Thus the latency of a pipelined data path can be arbitrarily small, provided that the resources are unlimited. In the case of loop folding, the latency (or loop length [24]) depends on the number of resources given and the structure of DFG.…”

“…Let oi --+ 0, denote a d-deg [24] data dependency between oi ( oi E F U,k) and oj and T;' be the time where 0, is executed at d iterations later. Suppose the loop length after folding is known to be I ; we have T; = + d .…”

High-level automatic pipelining for sequential circuits

“…Many synthesis tools target instruction-set architectures [10,4,3,14,15,1,9,2]; our tool, on the other hand, targets the more general class of sequential circuits. Other approaches start with a C program [8,5].…”

Low power pipelining of linear systems: A common operand centric approach

“…Two representative areas are code generation in compilers for embedded VLIW processors and high-level synthesis for ASIC design. Previous researches on pipelining of a linear system are primarily for throughput maximization under resource constraint [4], latency minimization under resource and throughput constraint [3], and joint throughput and latency optimization under resource constraint [5]. However, for the design of an embedded real time linear system that is gaining more and more attention nowadays, we often need to minimize the power consumption while considering the throughput and latency constraints, which has never been considered by the previous researches.…”