Low power pipelining of linear systems: A common operand centric approach

Kim, D.; Shin, D.; Choi, K.

doi:10.1109/lpe.2001.945405

Cited by 4 publications

(4 citation statements)

References 12 publications

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“…Su et al 23 suggest a scheduling technique to reduce the switching activities of address access during scheduling. Similarly, using list scheduling Kim et al 24 presented techniques to combine retiming with operand sharing scheduling. More recently, scheduling problem for low power design was formulated as a Traveling Salesman Problem (TSP) and the heuristics for TSP were used for the case of a single functional unit.…”

Section: Low Power Scheduling Problemmentioning

confidence: 99%

Early Quality Assessment for Low Power Behavioral Synthesis

Kursun¹,

Mukherjee²,

Memik³

2005

Journal of Low Power Electronics

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Fast and effective exploration at the early stages of the design flow can yield significant improvement in the quality of the design and substantial reduction in design time. In this paper, we present an efficient technique to evaluate the power dissipation of scheduled Data Flow Graphs (DFGs). Scheduling dictates the compatibility of operations with respect to their assignments to functional units. Generally for scheduled DFGs, this relation is captured in the form of a comparability graph. As a consequence, the topology of the comparability graph determines the solution space available to the subsequent binding stage. In this work, our main contribution is a technique to assess the inherent flexibility of the schedules we start with. We developed early evaluation metrics in order to assess the degree of flexibility inherent in an initial schedule that will eventually affect the quality of the binding solution. Every schedule is associated with a compatibility graph that represents the conflicts and compatibilities among operations with respect to possible binding decisions. Our metric based evaluation technique is based on several properties (such as edge connectivity, edge weight distribution, etc.) of these compatibility graphs. These metrics essentially reflect the amount of freedom that is provided to the binding stage, which enables early assessment and relative comparison of different possible schedules without actually performing the resource-binding step. Our experimental framework integrates scheduling, early metric-based power evaluation, low power binding and power driven iterative rescheduling stages. The correlation between early evaluation and the power measurements after binding is as high as 0.95 and greater than 0.75 for majority of test cases. Experimental results on DFGs from MediaBench suite demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement. Our results show that low power schedule selection is fast and effective. On average, the schedules selected by metric evaluation have 43% less power dissipation than schedules with iterative power improvement, based on a study set of 320 schedules. We also examined the thermal profile of the corresponding solutions. We observed that schedules selected with our metric evaluation technique have on average 12 C lower temperature, and the maximum on-chip temperatures are lower by 18 C compared to the overall average of all schedules. These thermal profiles are obtained using a functional unit-level thermal simulator after block-level floorplanning.

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Section: Low Power Scheduling Problemmentioning

confidence: 99%

Early Quality Assessment for Low Power Behavioral Synthesis

Kursun¹,

Mukherjee²,

Memik³

2005

Journal of Low Power Electronics

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“…Switching activities play a key role in the total power consumption [1,2]. Therefore, various techniques have been proposed to reduce power consumption by reducing switching activities [3][4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…In high-level synthesis, based on operand sharing approach, a loop pipelining methodology to reduce both latency and power is first proposed in [38]. Using similar approach, a loop pipelining technique is proposed to first minimize power and then maximize throughout in [10]. These techniques are based on operand sharing and cannot be directly used on multi-FU architectures.…”

Section: Introductionmentioning

confidence: 99%

Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture

Qiu

Liu

et al. 2008

J Sign Process Syst Sign Image Video Technol

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Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction.

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“…In HLS, based on operand sharing approach, a loop pipelining methodology to reduce both latency and power is first proposed in [14]. Using similar approach, a loop pipelining technique is proposed to first minimize power and then maximize throughput in [20]. These techniques are based on operand sharing and can not be directly used on multiple-functional-unit architectures.…”

Section: Introductionmentioning

confidence: 99%

Algorithms and analysis of scheduling for loops with minimum switching

Shao

Zhuge

Liu

et al. 2006

IJCSE

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Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on multiple-functional-unit architectures. We show that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial-time solvable if there is no resource constraints or only one functional unit(FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimize both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation at separate phases.

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Low power pipelining of linear systems: A common operand centric approach

Cited by 4 publications

References 12 publications

Early Quality Assessment for Low Power Behavioral Synthesis

Early Quality Assessment for Low Power Behavioral Synthesis

Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture

Algorithms and analysis of scheduling for loops with minimum switching

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