Loop parallelization and pipelining implementation of AES algorithm using OpenMP and FPGA

Banu, J. Saira; Vanitha, M.; Vaideeswaran, J.; Subha, S.

doi:10.1109/ice-ccn.2013.6528547

Cited by 8 publications

(4 citation statements)

References 10 publications

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“…Two implementations of the AES algorithm were introduced; the first one was based on the basic architecture of the AES and the second one on the sub-pipelined architecture. Banu et al [23] proposed high throughput hardware and software implementation of the AES algorithm. The hardware implementation was based on architectural optimization techniques like pipelining, loop unrolling and iterative design to increase the speed by processing multiple rounds simultaneously.…”

Section: Previous Workmentioning

confidence: 99%

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

Oukili

Bri

2017

TELKOMNIKA

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The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.

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Section: Previous Workmentioning

confidence: 99%

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

Oukili

Bri

2017

TELKOMNIKA

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“…In addition, Banu et al accelerated AES by combining hardware parallelism made by field‐programmable gate array and software parallelism (i.e., OpenMP). Currently, Liu and Baas parallelized AES on an Asynchronous Array of Simple Processors and gained better performance with higher energy efficiency.…”

Section: Related Workmentioning

confidence: 99%

“…In some typical applications, massive users' data are usually short but may be different in length. For example, in a secure socket layer (SSL), transferring data usually varies from 35 to 150KB, but different user's data may have a different length . If we just use GPU parallelism or CPU parallelism to accelerate encrypting in this situation, it does not fully utilize the computing performance of a CPU or GPU, because a GPU or CPU often encounter these short plaintexts.…”

Section: Introductionmentioning

confidence: 99%

Practical parallel AES algorithms on cloud for massive users and their performance evaluation

Fei

et al. 2015

Concurrency and Computation

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Summary Many e‐business or social network servers have been constructed on cloud. On such open environments, private data of massive users have to be protected by encrypting, such as using Advanced Encryption Standard (AES), and furthermore, this process must be finished in a short time for users' better experience. This gives huge pressure on cloud servers, especially common servers, such as web servers. We urgently need an inexpensive and highly efficient method to relieve cloud servers' pressure. Fortunately, many cores of a graphics processing unit (GPU) can undertake this hard mission because of stronger computing power and lower price. The GPU environments can be virtualized on demand by cloud through the vCUDA technology. Of course, for those clouds not equipped with a GPU, a central processing unit (CPU) can still work as multithreads in parallel. Thus, in a cloud, AES can be parallelized using many cores of a GPU or multicores of a CPU with high efficiency and low cost. For typical cloud applications, such as web services, there are massive users and each one has short plaintext. If we simply parallelize AES in such an application, we cannot obtain better performance because of the GPU's extra data transferring cost. Thus, we coalesce the massive users' data and cut these data into same‐length slices for improving the performance of parallel AES as much as possible. So we design six parallel AES algorithms using GPU parallelism or CPU parallelism, which differ in parallel scope and whether data are coalesced or cut to slices. Specifically, they are coalescent and sliced GPU (GCS), coalescent and unsliced GPU, uncoalescent GPU, coalescent and sliced CPU, coalescent and unsliced CPU, and uncoalescent CPU. Moreover, we implement them on two representative platforms and evaluate their performance. Through comparing their performance, GCS has the best performance among these algorithms. In a cloud with Nvidia GPUs, GCS is a more powerful algorithm for massive users' data encrypting, relatively. Copyright © 2015 John Wiley & Sons, Ltd.

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“…LEA has 128-bit block size with 128, 192, 256-bit key sizes and rounds 24, 28 and 32 respectively. LEA supports simple ARX (addition rotation XOR ) operation, LEA is not using complex S-box structure like AES [4] hence it will give high-speed operation.LEA is independent of all attacks for block ciphers, which makes it more suitable for those places where we need both security with high performance. LEA uses some arbitrary constants in its algorithm which makes it more efficient to provide confusion and diffusion in encryption.…”

Section: Introductionmentioning

confidence: 99%

LEA 192: High Speed Architecture of Lightweight Block Cipher

2019

IJITEE

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High-throughput lightweight cryptography calculation is the need of the present world to convey between two asset obliged devices Pipelining is the technique have been used to achieve high throughput. In this paper we have target to lightweight block cipher LEA. Block size of LEA is 128 and key size 128, 192, and 256 bit. In this paper we have focus on LEA architecture for 192- bit key size and achieve very good throughput. This method has a higher capability of throughput as compared to previous LEA ciphers. Proposed work is 56% improved version of compared paper for respective Speed and area also less than previous architecture. Graph representation have been shown of different matrices and comparison.

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Loop parallelization and pipelining implementation of AES algorithm using OpenMP and FPGA

Cited by 8 publications

References 10 publications

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

Practical parallel AES algorithms on cloud for massive users and their performance evaluation

LEA 192: High Speed Architecture of Lightweight Block Cipher

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