Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Mopuri, Suresh; Acharyya, Amit

doi:10.1007/s00034-021-01738-1

Cited by 5 publications

(13 citation statements)

References 22 publications

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“…We replicated the architectures in [8,10,11] with the same fractional bit widths of the input and output and a precision comparable to that of our design. We list the parameters and errors in Table 1.…”

Section: Implementation Results and Comparisonmentioning

confidence: 99%

“…To compare our design with the architectures in [8,10,11], we replicated these three hardware implementations with errors at the same level as in our design. The synthesis results are listed in Table 2.…”

Section: Details Of Hardware Implementationmentioning

confidence: 99%

“…When implemented in software, the complex square root operation requires a long execution time, leading to difficulty in meeting requirements for high speed and low latency. Therefore, various kinds of hardware implementations have been proposed for computing complex square roots, such as the digit-recurrence algorithm [5][6][7], 2D cubic convolution [8], and the coordinate rotation digital computer (CORDIC) method [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…Ref. [11] proposed a CORDIC-based very-large-scale integration (VLSI) architecture design methodology for complex square root computation that is independent of angle computation. The fully pipelined structures (yielding a valid output in every cycle) based on the CORDIC algorithm that are presented in [10,11] perform well in terms of throughput, but are weak in latency because of their numerous iterations.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method

Wang

Liang

et al. 2023

Electronics

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In this paper, we propose a methodology for computing the square root of a complex number based on a piecewise linear (PWL) approximation method. The proposed method relies on a software-based segmentor that automatically divides the three real square root functions used in complex square root computation into the fewest segments with a predefined fractional bit width and maximum absolute error (MAE). The coefficients, including the start point, end point, slope and y-intercept of each segment, are stored for use in the implementation of the hardware design. The proposed fully pipelined circuit is coded in the Verilog hardware description language (HDL). The results of synthesis in TSMC (Taiwan Semiconductor Manufacturing Company) 65-nm CMOS technology show that our design achieves savings of 64.21% in area, 16.67% in delay and 65.08% in power compared to the existing methods. Moreover, implementation results on an FPGA (Field-Programmable Gate Array) platform (XC7Z020-CLG400) show that the proposed design reduces the number of LUTs by 29.38%, delay by 28.57% and power consumption by 53.47%.

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Section: Implementation Results and Comparisonmentioning

confidence: 99%

Section: Details Of Hardware Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method

Wang

Liang

et al. 2023

Electronics

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“…The CORDIC algorithm was first proposed in 1959 by E. Volder for computing trigonometric functions, multiplication and division [11,12]. To expand the usage areas, the CORDIC algorithm is applied in the computation of logarithms, exponentials, square roots, arbitrary Nth root, complex operations [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. In the implementation of the CORDIC algorithm, the type of computation (addition or subtraction) in the iteration is determined by the rotation direction.…”

Section: Introductionmentioning

confidence: 99%

An optimized hardware implementation of the CORDIC algorithm

Lyu

Wang

et al. 2022

IEICE Electron. Express

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In this paper, we propose a software-based simulator and an optimized hardware implementation of the CORDIC algorithm. The number of iterations and the bit width are selected by their relationship calculated by the simulator to satisfy precision requirement. In the proposed hardware implementation, the addition and subtraction operations share the hardware resources. The two's complement is calculated in two steps: inverting and adding one. The adding one operation is integrated in the addition component of the iteration. In addition, a 3:2 compressor is used to reduce the number of adders, and a carry look-ahead adder is used to reduce the critical path. The synthesized results show that when compared with state-of-the-art designs, our method reduces the area by 53.79% and the delay by 58.97% while maintaining the same precision.

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Low-Complexity Square-Root Unscented Kalman Filter Design Methodology

Dutt

Acharyya

2023

Circuits Syst Signal Process

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Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Cited by 5 publications

References 22 publications

An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method

An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method

An optimized hardware implementation of the CORDIC algorithm

Low-Complexity Square-Root Unscented Kalman Filter Design Methodology

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