Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR

A High Phase Detection Density and Low Space Complexity Mueller-Muller Phase Detector for DB PAM-4 Wireline Receiver

“…This PD can provide phase-detection information in 50% of the data transitions in PAM-4, and the phase-detection density is 50%, which is the same as the typical density under NRZ data [8]; the phase-detection density of PAM-4 MMPD [11] is about 43.75%. The phase-detection density of DB PAM-4 is about 65% and 25% with BBPD [16]. As shown in Table 2, DB PAM-4 improves the phase by about 30% compared to 50% of the classical phase-detection density and 160% compared to BBPD.…”

“…In order to improve the insufficient CDR phase-detection density at high loop speed, the MMPD is redesigned for DB PAM-4. With reference to the CDR loop of DB PAM-4 based on BBPD [16], this MMPD is introduced later.…”

“…The eye diagram of the 3 UI of DB PAM-4 is shown in the Figure 3. Compared with 3 UI PAM-4, DB PAM-4 has an increase in data conversion edge from 64 cases to 175 cases, while only 37 objects need to be discriminated in BBPD mode [16], the complexity of phase-detection process increases significantly, mainly in the space complexity. To solve the complex phase-detection problem of DB PAM-4, the waveform sifting technology used to transform the phase-detection object into five types of judgment processes based on trends, which significantly reduces the space complexity of the phasedetection logic process.…”

“…The early probability is Pr(early|ϕ 0 ), and the late probability is Pr(late|ϕ 0 ). When the average value of the phase difference is ϕ 0 , the expression of the average output voltage is µ [16]:…”

“…The original structure of the sampler plus CDR for Data Retiming under pam-4 modulation [11][12][13] is not applicable to the current modulation mode. The analog to digital converter (ADC) + digital signal processing (DSP) architecture is a modular architecture, in which the output clock of the phase interpolator (PI) controls the high-speed ADC for data sampling, and the DSP controls the clock phase of the PI [14][15][16], which is applicable to DB pam-4. ADC integrate to the system through intellectual property (IP) core for data sampling and quantization.…”