Low-complexity bit-parallel systolic architecture for computing AB/sup 2/+C in a class of finite field GF(2/sup m/)

Abstract

An algorithm for computing + over a finite field (2 ) is presented using the properties of the irreducible all one polynomial of degree . Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems.Index Terms-All one polynomial (AOP), finite field, latency, systolic multiplier.

Low-Complexity One-Dimensional Parallel Semi-Systolic Structure for Field Montgomery Multiplication Algorithm Perfect for Small IoT Edge Nodes

“…Bit-serial multipliers are space-efficient and have significant savings in power consumption, but they are slow and require m clock cycles to multiply two elements [2,22,23]. In contrast, bit-parallel multipliers require excessive hardware cost and high power consumption, but produce the result in one clock cycle [4,5,8,[24][25][26][27][28][29]. Systolic/semi-systolic serial or parallel multiplier architectures are more suitable for VLSI implementation than the other types of conventional implementations.…”

“…The equally spaced and AOP polynomials were used as the foundation for bit-parallel's systolic multiplier structure proposed by Lee et al [24,25]. In 2005, Lee et al [26] suggested a mapping approach in order to reduce the complexity of the AOP-based bit-parallel systolic multiplier.…”