Low-Complexity Concatenated LDPC-Staircase Codes

Abstract

A low-complexity soft-decision concatenated FEC scheme, consisting of an inner LDPC code and an outer staircase code is proposed. The inner code is tasked with reducing the bit error probability below the outer-code threshold. The concatenated code is obtained by optimizing the degree distribution of the inner-code ensemble to minimize estimated data-flow, for various choices of outer staircase codes. A key feature that emerges from this optimization is that it pays to leave some inner codeword bits completely uncoded, thereby greatly reducing a significant portion of the decoding complexity. The trade-off between required SNR and decoding complexity of the designed codes is characterized by a Pareto frontier. Computer simulations of the resulting codes reveals that the net coding-gains of existing designs can be achieved with up to 71% reduction in complexity. A hardware-friendly quasi-cyclic construction is given for the inner codes, which can realize an energy-efficient decoder implementation, and even further complexity reductions via a layered message-passing decoder schedule. * The authors are with the Edward S. Rogers Sr.This paper continues the work of Zhang and Kschischang [6] on designing low-complexity concatenated FEC schemes for applications with high throughput. Their design consists of an inner soft-decision low-density generator-matrix (LDGM) code concatenated with an outer hard-decision staircase code. The degree distribution of the inner LDGM code ensemble is obtained by solving an optimization problem, minimizing the estimated data-flow of the inner-code decoder, while searching a table of staircase codes to find the optimal inner and outer code pair. At 20% OH, the codes proposed in [6] can achieve up to 46% reduction in complexity, when compared with other low-complexity designs.In this paper, we adopt the concatenated FEC structure of [6], but we consider a different ensemble of inner codes. The task of the inner code, similar to that of [6], is to reduce the bit error rate (BER) of the bits transferred to the outer staircase code to below the threshold, which enables the outer code to take the BER further down, below 10 −15 , as required by OTNs. We re-design the inner code to further reduce its data-flow, thereby achieving an FEC solution with even lower complexity than the codes reported in [6].A key characteristic that emerges from the re-designed inner-code optimization is that some inner codeword bits remain uncoded! These bits bypass the inner code, and are protected only by the outer-code. We propose a method to analyze and optimize the inner-code ensemble, and show that the resulting codes can reduce the inner-code data-flow by up to 71%, when compared to [6]. We show that, when block length is sufficiently large, codes generated according to the obtained inner-code ensembles perform as expected, verifying the design approach.To realize a pragmatic decoder implementation, we construct quasi-cyclic (QC) codes of practical length, generated according to the obtained inner-code ensembl...

On Low-Complexity Decoding of Product Codes for High-Throughput Fiber-Optic Systems

“…Thus, for components codes where t is small (e.g., 2, 3, or 4), as the ones considered in this paper and of practical use for high-throughput fiber-optic communications, the list size and corresponding cost per component decoding in GMD decoding is only a fraction of that of TPD. Moreover, iGMDD-SR also relaxes the computational requirements when computing the extrinsic soft-output information for each code bit compared to TPD by using the heuristic update equation in (5).…”

“…The recent years have seen an increasing interest in the research community in closing the gap between the performance of HD-FEC and SD-FEC, while keeping the decoding complexity low. An interesting line of research is to concatenate an inner SD-FEC code, e.g., a low-density parity-check (LDPC) code decoded via belief propagation, with an outer staircase code [4], [5]. Another alternative, investigated by the authors in [17] and [18], is to improve the performance of iBDD.…”

“…, µ r,( ) n,j ). GMD decoding is performed based on R ( ) :,j = B(μ c,( ) j ) and |μ c,( ) j|.The soft output of the j-th column decoder is formed similar to(5) and the resulting soft output vector is denoted by µ ), where µ c, j,i corresponds to the message from column CN j to row CN i. After decoding all column component codes, we setμ r,( +1) i ) and the iterative process continues until a maximum number of iterations is reached.…”

Energy-Efficient High-Throughput VLSI Architectures for Product-Like Codes

“…Since throughput aspects are central in this work, it is worthwhile to note that the structure of product and staircase codes lends itself to block-parallel high-throughput decoding. Because of this property, staircase codes have recently received significant attention within the fiber-optic communication research community as a promising alternative for power-constrained applications: Prior art includes staircasecode optimization, both as stand-alone codes [7], [8] and in concatenated schemes [9], [10], but to the best of our knowledge, no VLSI implementations have been published in the open literature, save for our own previous work [11].…”

Rate-Adaptive Coded Modulation with Geometrically-shaped Constellations

“…Staircase codes (SCCs) [6] are a family of popular high-performance HD-FEC codes. Recently, low-complexity concatenated FEC schemes have been studied to combine the advantages of soft-and harddecision decoders [7]. Probabilistic and geometric shaping [8]- [13] have been studied to increase the gain for different transmission distance applications.…”