Low-complexity DFT-pair carrier acquisition

Jayasimha, S.; Jyothendar, P.; Bhargav, B. Satish

doi:10.1109/ncc.2013.6488000

Cited by 1 publication

(1 citation statement)

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“…Early-late gate synchronizer is another widely used closed-loop CDR circuit [29][30][31]. This method performs two integrations of the received signal over two different periods of the symbol interval.…”

Section: Related Workmentioning

confidence: 99%

A small fully digital open‐loop clock and data recovery circuit for wired BANs

Derogarian

Ferreira

Tavares

2015

Circuit Theory & Apps

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This paper proposes a new open-loop and low complexity (small size) fast-lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open-loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase-locked loops or delay-locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non-return-to-zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal-oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35-data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption.

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Section: Related Workmentioning

confidence: 99%