Low complexity modified constant Log-Map algorithm for radix-4 turbo decoder

Abstract

Turbo decoding for 3GPP-LTE wireless communication standard is most challenging task to reduce computational complexity. This paper presents 8-state trellis VHDL implementation of radix-2 and radix-4 form. In a practical system, the original MAP algorithm is too complex for implementation. All the branch metrics required for calculating LLR values are stored in a RAM. Max * function is implemented with correction factor to improve performance. The proposed, implemented algorithm is almost identical to max * function. With increasing demand for different data rate and services for communication system reconfigurability is important. So implementation is targeted towards Xilinx Virtex E FPGAs. The turbo decoder uses soft in soft out (SISO) decoders to decode one code word.

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

“…At the same time, we also propose the Nor-LUT-Log-MAP algorithm, which uses the Nor-Log-MAP algorithm to calculate forward-state and backward-state metrics as well as the LUT-Log-MAP algorithm to compute external information and posteriori information. As shown in Figure 9, the decoding performance of the Nor-LUT-Log-MAP algorithm is less than that of the LUT-Nor-Log-MAP algorithm, and it can be concluded that the forward-state and backward-state metric computation requires a better algorithm in the turbo decoding process [18]. In [10], Sun et al proposed FFU to compute the metrics of every state.…”